Product Info

ManualsBrandslantronix ManualsElectronicsLTE Cat M1 & Cat NB2 & EGPRS Module

BG95 Series

Hardware Design

LPWA Module Series

Rev. BG95_Series_Hardware_Design_V1.2

Date: 2020-07-06

Status: Released

Summary of content (109 pages)

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BG95 Series Hardware Design LPWA Module Series Rev. BG95_Series_Hardware_Design_V1.
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LPWA Module Series BG95 Series Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Lantronix Corporate Headquarters 7535 Irvine Center Drive, Suite 100 Irvine, CA 92618 USA Tel: +1 (800) 526-8766 sales@lantronix.com Or our local office. For more information, please visit: https://www.lantronix.com/ GENERAL NOTES Lantronix, Inc. OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS.
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LPWA Module Series BG95 Series Hardware Design About the Document Revision History Version Date Author Description 1.0 2019-09-30 Lyndon LIU/ Garey XIE Initial Lyndon LIU/ Garey XIE 1. Updated the GNSS function into an optional feature. 2. Updated the LTE Power Class 5 to 21 dBm. 3. Added the parameters (power supply, operating frequency, output power, etc.) of BG95-M4 and BG95-M5. 4. Updated the transmitting power parameters in Table 3 and Table 40. 5.
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LPWA Module Series BG95 Series Hardware Design 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. BG95_Series_Hardware_Design configuration. Added the power supply range of BG95-M4, and the typical power supply of BG95-MF. Added the function diagram of BG95-M4, BG95-M5, BG95-M6 and BG95-MF in Chapter 2.3. Enabled pin 56 (ANT_WIFI) for BG95-MF. Updated the GNSS performance in Table 30. Added the current consumption values of BG95-M1, BG95-M2, BG95-M5 and BG95-M6 in Chapter 6.4.
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LPWA Module Series BG95 Series Hardware Design Contents About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 4 Table Index ...............................................................................................................................
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LPWA Module Series BG95 Series Hardware Design 3.17. ADC Interfaces .......................................................................................................................... 58 3.18. GPIO Interfaces ........................................................................................................................ 59 3.19. GRFC Interfaces ....................................................................................................................... 61 4 GNSS Receiver .........
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LPWA Module Series BG95 Series Hardware Design Table Index Table 1: Version Selection for BG95 Series Modules ............................................................................... 14 Table 2: Frequency Bands and GNSS Types of BG95 Series Modules ................................................... 14 Table 3: Key Features of BG95 Series Modules ....................................................................................... 17 Table 4: Definition of I/O Parameters...........................
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LPWA Module Series BG95 Series Hardware Design Table 42: BG95-M3 Current Consumption (3.8 V Power Supply, Room Temperature) ........................... 78 Table 43: BG95-M5 Current Consumption (3.8 V Power Supply, Room Temperature) ........................... 80 Table 44: BG95-M6 Current Consumption (3.8 V Power Supply, Room Temperature) ........................... 82 Table 45: GNSS Current Consumption of BG95-M1/-M2 (3.3 V Power Supply, Room Temperature) ....
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LPWA Module Series BG95 Series Hardware Design Figure Index Figure 1: Functional Diagram of BG95-M3 ................................................................................................ 20 Figure 2: Pin Assignment (Top View) ........................................................................................................ 25 Figure 3: Sleep Mode Application via UART .............................................................................................
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LPWA Module Series BG95 Series Hardware Design Figure 42: JATE/TELEC Certification ID of BG95-M5 .............................................................................
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LPWA Module Series BG95 Series Hardware Design 1 Introduction This document defines BG95 series module and describes its air interface and hardware interfaces which are connected with your applications. This document helps you quickly understand the interface specifications, electrical and mechanical details, as well as other related information of BG95 series module. To facilitate application designs, it also includes some reference designs for your reference.
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LPWA Module Series BG95 Series Hardware Design 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.
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LPWA Module Series BG95 Series Hardware Design radioélectrique subi, même si le brouillage est susceptible d’en compromettre le fonctionnement." Déclaration sur l'exposition aux rayonnements RF The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the user’s body and must not transmit simultaneously with any other antenna or transmitter.
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LPWA Module Series BG95 Series Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating BG95 series module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals supplied with the product. If not so, Lantronix, Inc.
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LPWA Module Series BG95 Series Hardware Design 2 Product Concept 2.1. General Description BG95 is a series of embedded IoT (LTE Cat M1, LTE Cat NB2 and EGPRS) wireless communication modules. It provides data connectivity on LTE-FDD and GPRS/EGPRS networks, and supports half-duplex operation in LTE network. It also provides GNSS and voice* 1) functionality to meet your specific application demands.
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LPWA Module Series BG95 Series Hardware Design B66/B85 BG95-M2 Cat M1: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B26/B27/B28/ B66/B85 Cat NB2: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B28/B66/B71/ B85 BG95-M3 Cat M1: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B26/B27/ B28/B66/B85 Cat NB2: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B28/B66/B71/ B85 EGPRS: 850/900/1800/1900 MHz BG95-N1 Cat NB2 Only: LTE FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B28/B66/B71/
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LPWA Module Series BG95 Series Hardware Design Cat NB2: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B28/B66/B71/ B85 EGPRS: 850/900/1800/1900 MHz BG95-M6 Cat M1: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B26/B27/B28/ B66/B85 Cat NB2: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B28/B66/B71/ B85 BG95-MF Cat M1: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B26/B27/ B28/B66/B85 Cat NB2: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B28/B66/B71/ B85 Wi-Fi (For Position
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LPWA Module Series BG95 Series Hardware Design It supports internet service protocols l ike TCP, UDP and PPP. Based on extended AT commands developed by Lantronix, Inc., you can use these internet service protocols easily. 2.2. Key Features The following table describes the detailed features of BG95 series modules. Table 3: Key Features of BG95 Series Modules Features Details Power Supply BG95-M1/-M2/-N1:  Supply voltage 1): 2.6–4.8 V  Typical supply voltage: 3.
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LPWA Module Series BG95 Series Hardware Design  GSM Features Cat NB2: Max. 127 kbps (DL)/158.5 kbps (UL) GPRS:  Support GPRS multi-slot class 33 (33 by default)  Coding scheme: CS-1, CS-2, CS-3 and CS-4  Max. 107 kbps (DL), Max. 85.6 kbps (UL) EDGE:  Support EDGE multi-slot class 33 (33 by default)  Support GMSK and 8-PSK for different MCS (Modulation and Coding Scheme)  Downlink coding schemes: MCS 1-9  Uplink coding schemes: MCS 1-9  Max. 296 kbps (DL), Max. 236.
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LPWA Module Series BG95 Series Hardware Design GNSS   AT Commands 3GPP TS 27.007 and 3GPP TS 27.005 AT commands, as well as Lantronix, Inc. enhanced AT commands Network Indication One NET_STATUS pin for network connectivity status indication Antenna Interfaces Main antenna (ANT_MAIN) and GNSS antenna (ANT_GNSS) interfaces Physical Characteristics   Dimensions: (23.6 ±0.15) mm × (19.9 ±0.15) mm × (2.2 ±0.20) mm Weight: approx. 2.
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LPWA Module Series BG95 Series Hardware Design Figure 1: Functional Diagram of BG95-M3 Figure 2: Functional Diagram of BG95-M1/-M2/-N1 BG95_Series_Hardware_Design 20 / 106
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LPWA Module Series BG95 Series Hardware Design MAIN_ANT ANT_GNSS Coupler SAW Switch LNA LPF VBAT_RF TRx GNSS SAW B31PA LTE LB TX LPF Tx Switch/PA/Transceiver VBAT_BB Control IQ PWRKEY PMIC Control RESET_N Baseband PON_TRIG ADC1 19.
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LPWA Module Series BG95 Series Hardware Design ANT_GNSS ANT_MAIN SAW Coupler LNA VBAT_RF 4G PA SAW LTE Tx GNSS LTE Rx Switch/PA/Transceiver VBAT_BB Control IQ PWRKEY PMIC Control RESET_N Baseband PON_TRIG ADC1 19.2M XO ADC0 VDD_EXT USB (U)SIM PCM I2C GPIOs UARTs STATUS NET_STATUS Figure 5: Functional Diagram of BG95-M6 ANT_WIFI ANT_GNSS ANT_MAIN SAW LDO VBAT_RF 3.
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LPWA Module Series BG95 Series Hardware Design NOTES 1. eSIM function is optional. If eSIM is selected, then any external (U)SIM cannot be used. BG95-M5 and BG95-M6 do not support eSIM. 2. PWRKEY output voltage is 1.5 V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, never pull down PWRKEY to GND permanently. 3. RESET_N connects directly to PWRKEY inside the module. 4.
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LPWA Module Series BG95 Series Hardware Design 3 Application Interfaces BG95 series is equipped with 102 LGA pads for connection to various cellular application platforms.
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LPWA Module Series BG95 Series Hardware Design Figure 2: Pin Assignment (Top View) NOTES 1. 1) Only BG95-MF supports ANT_WIFI (pin 56).
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LPWA Module Series BG95 Series Hardware Design 2. 3. 4. 5. 6. 7. 8. 9. 2) BG95-MF does not support GPIO3 and GPIO4 interfaces (pin 64 and pin 65). BG95-M4 does not support GRFC interfaces (pin 83 and pin 84). Do not use ADC0 and ADC1 simultaneously, as ADC1 connects directly to ADC0 inside the module. BG95 series module supports use of only one ADC interface at a time: either ADC0 or ADC1. PWRKEY output voltage is 1.5 V because of the voltage drop inside the Qualcomm chipset.
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LPWA Module Series BG95 Series Hardware Design Table 5: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment BG95-M1/-M2/-N1: Vmax = 4.8 V Vmin = 2.6 V Vnorm = 3.3 V VBAT_BB 32, 33 PI Power supply for the module’s baseband part BG95-M3/-M5/-M6 Vmax = 4.3 V Vmin = 3.3 V Vnorm = 3.8 V See NOTE 1 BG95-M4: Vmax = 4.2 V Vmin = 3.2 V Vnorm = 3.8 V BG95-MF: Vnorm = 3.8 V BG95-M1/-M2/-N1: Vmax = 4.8 V Vmin = 2.6 V Vnorm = 3.
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LPWA Module Series BG95 Series Hardware Design 58, 59, 61, 62, 67–74, 79–82, 89–91, 100–102 Turn on/off I/O Description DC Characteristics Comment 15 DI Turns on/off the module Vnorm = 1.5 V VILmax = 0.45 V Never pull down PWRKEY to GND permanently. Pin Name Pin No. I/O Description DC Characteristics Comment RESET_N 17 DI Resets the module Vnorm = 1.5 V VILmax = 0.45 V Pin Name PWRKEY Pin No. Reset Status Indication Pin Name Pin No.
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LPWA Module Series BG95 Series Hardware Design VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep this pin open. Only 1.8 V (U)SIM card is supported. USIM_DET 42 DI (U)SIM card hot-plug detection USIM_VDD 43 PO (U)SIM card power supply Vmax = 1.9 V Vmin = 1.7 V USIM_RST 44 DO (U)SIM card reset VOLmax = 0.45 V VOHmin = 1.35 V USIM_DATA 45 IO (U)SIM card data VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V VOLmax = 0.
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LPWA Module Series BG95 Series Hardware Design MAIN_RI 39 DO Main UART ring indication VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. If unused, keep this pin open. I/O Description DC Characteristics Comment DI Debug UART receive VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep this pin open. DO Debug UART transmit VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. If unused, keep this pin open.
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LPWA Module Series BG95 Series Hardware Design I2C Interface* Pin Name I2C_SCL I2C_SDA Pin No. 40 41 I/O Description DC Characteristics Comment I2C serial clock (for external codec) External pull-up resistor is required. 1.8 V only. If unused, keep this pin open. OD I2C serial data (for external codec) External pull-up resistor is required. 1.8 V only. If unused, keep this pin open. OD Antenna Interfaces Pin Name Pin No.
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LPWA Module Series BG95 Series Hardware Design GPIO3 2) GPIO4 2) GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 64 65 66 85 86 87 88 IO IO IO IO IO IO IO General-purpose input/output VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep this pin open. General-purpose input/output VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep this pin open.
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LPWA Module Series BG95 Series Hardware Design Pin Name Pin No. I/O Description DC Characteristics Comment Voltage range: 0.1–1.8 V ADC0 24 AI General-purpose ADC interface ADC1 2 AI General-purpose ADC interface Voltage range: 0.1–1.8 V Do not use ADC0 and ADC1 simultaneously. If unused, keep these pins open. I/O Description DC Characteristics Comment 1.8 V power domain. Pulled up by default. When it is in low voltage level, the module can enter airplane mode.
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LPWA Module Series BG95 Series Hardware Design If unused, keep this pin open. RESERVED Pins Pin Name Pin No. RESERVED 11–14, 16, 51, 57, 63, 76–78, 92–95, 97–99 I/O Description Reserved DC Characteristics Comment Keep these pins open. NOTES 1. 1) Only BG95-MF supports ANT_WIFI (pin 56). 2. 2) BG95-MF does not support GPIO3 and GPIO4 interfaces (pin 64 and pin 65). 3. 3) BG95-M4 does not support GRFC interfaces (pin 83 and pin 84). 4.
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LPWA Module Series BG95 Series Hardware Design Table 6: Overview of BG95 Operating Modes Mode Normal Operation Details Connected Network has been connected. In this mode, the power consumption may vary with the network setting and data transfer rate. Idle Software is active. The module remains registered on network, and it is ready to send and receive data.
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LPWA Module Series BG95 Series Hardware Design Hardware: W_DISABLE#* is pulled up by default. Driving it low makes the module enter airplane mode. Software: AT+CFUN= provides choice of the functionality level, through setting into 0, 1 or 4.  AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled.  AT+CFUN=1: Full functionality mode (by default).  AT+CFUN=4: Airplane mode. RF function is disabled. NOTES 1. 2. 3.
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LPWA Module Series BG95 Series Hardware Design 3.4.3. Extended Idle Mode DRX (e-I-DRX) The module (UE) and the network may negotiate over non-access stratum signalling the use of e-I-DRX for reducing its power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value.
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LPWA Module Series BG95 Series Hardware Design Figure 3: Sleep Mode Application via UART    When the module has URC to report, MAIN_RI signal wakes up the host. See Chapter 3.15 for details about MAIN_RI behavior. Driving MAIN_DTR low wakes up the module. AP_READY* detects the sleep state of the host (can be configured to high level or low level detection). See AT+QCFG="apready" command in document [2] for details. NOTE “*” means under development. 3.5. Power Supply 3.5.1.
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LPWA Module Series BG95 Series Hardware Design Table 7: VBAT and GND Pins Pin Name VBAT_RF VBAT_BB GND Pin No. 52, 53 32, 33 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 67–74, 79–82, 89–91, 100–102 Description Power supply for the module’s RF part Power supply for the module’s baseband part Ground Module Min. Typ. Max. Unit BG95-M1/-M2/-N1 1) 2.6 3.3 4.8 V BG95-M3/-M5/-M6 3.3 3.8 4.3 V BG95-M4 3.2 3.8 4.2 V BG95-MF TBD 3.8 TBD V BG95-M1/-M2/-N1 1) 2.6 3.3 4.
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LPWA Module Series BG95 Series Hardware Design drop below 3.2 V.  BG95-MF: The typical power supply of BG95-MF is 3.8 V. The following figure shows the voltage drop during burst transmission in 2G network of BG95-M3/-M5. The voltage drop is less in LTE Cat M1 and/or LTE Cat NB2 networks. Burst Transmission Burst Transmission VBAT Ripple Drop Min.3.
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LPWA Module Series BG95 Series Hardware Design 3.5.3. Monitor the Power Supply AT+CBC command can be used to monitor the VBAT_BB voltage value. For more details, see document [2]. 3.6. Turn on and off Scenarios 3.6.1. Turn on Module Using the PWRKEY Pin The following table shows the pin definition of PWRKEY. Table 8: Pin Definition of PWRKEY Pin Name PWRKEY Pin No. 15 Description DC Characteristics Comment Turns on/off the module Vnorm = 1.5 V VILmax = 0.45 V The output voltage is 1.
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LPWA Module Series BG95 Series Hardware Design Figure 7: Turn on the Module Using Keystroke The power on scenario is illustrated in the following figure. Figure 8: Power-on Timing NOTES 1. Make sure that VBAT is stable before pulling down PWRKEY pin and keep the interval no less than 30 ms.
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LPWA Module Series BG95 Series Hardware Design 2. PWRKEY output voltage is 1.5 V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, never pull down PWRKEY to GND permanently. 3.6.2. Turn off Module Either of the following methods can be used to turn off the module:   Turn off the module through PWRKEY. Turn off the module through AT+QPOWD command. 3.6.2.1.
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LPWA Module Series BG95 Series Hardware Design 3.7. Reset the Module RESET_N is used to reset the module. Due to platform limitations, the chipset has integrated the reset function into PWRKEY, and RESET_N connects directly to PWRKEY inside the module. The module can be reset by driving RESET_N low for 2–3.8 s. Table 9: Pin Definition of RESET_N Pin Name Pin No. Description DC Characteristics Comment RESET_N 17 Resets the module VILmax = 0.
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LPWA Module Series BG95 Series Hardware Design S2 RESET_N TVS Close to S2 Figure 12: Reference Circuit of RESET_N by Using Button NOTE Please assure that there is no large capacitance on RESET_N pin. 3.8. PON_TRIG Interface BG95 provides one PON_TRIG pin which is used to wake up the module from PSM. When the pin detects a rising edge, the module is woken up from PSM. Table 10: Pin Definition of PON_TRIG Interface Pin Name PON_TRIG Pin No.
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LPWA Module Series BG95 Series Hardware Design VDD_1V8 10K 10K PON_TRIG_EXT 100K 100K PON_TRIG Figure 13: Reference Circuit of PON_TRIG NOTE VDD_1V8 is provided by an external LDO. 3.9. (U)SIM Interface BG95 supports 1.8 V (U)SIM card only. The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Table 11: Pin Definition of (U)SIM Interface Pin Name Pin No. I/O Description Comment USIM_DET 42 DI (U)SIM card hot-plug detection 1.8 V power domain.
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LPWA Module Series BG95 Series Hardware Design BG95 supports (U)SIM card hot-plug via the USIM_DET pin, and both high and low level detections are supported. The function is disabled by default, and see AT+QSIMDET command in document [2] for more details. The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector.
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LPWA Module Series BG95 Series Hardware Design       Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200 mm as possible. Keep (U)SIM card signals away from RF and VBAT traces. Assure the ground between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5 mm to maintain the same electric potential.
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LPWA Module Series BG95 Series Hardware Design GND 3 Ground For more details about USB 2.0 specification, please visit https://www.usb.org/. The USB interface is recommended to be reserved for firmware upgrade in application designs. The following figure shows a reference design of USB interface. Figure 16: Reference Design of USB Interface In order to ensure the integrity of USB data line signal, components R1 and R2 should be placed close to the module.
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LPWA Module Series BG95 Series Hardware Design 3.11. UART Interfaces The module provides three UART interfaces: the main UART, debug UART and the GNSS UART interfaces. Features of them are illustrated below:    The main UART interface supports 9600 bps, 19200 bps, 38400 bps, 57600 bps, 115200 bps, 230400 bps, 460800 bps and 921600 bps baud rates, and the default is 115200 bps. It is used for data transmission and AT command communication, and supports RTS and CTS hardware flow control.
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LPWA Module Series BG95 Series Hardware Design Table 14: Pin Definition of Debug UART Interface Pin Name Pin No. I/O Description Comment DBG_RXD 22 DI Debug UART receive 1.8 V power domain DBG_TXD 23 DO Debug UART transmit 1.8 V power domain Table 15: Pin Definition of GNSS UART Interface Pin Name Pin No. I/O Description Comment GNSS_TXD 27 DO GNSS UART transmit BOOT_CONFIG. Do not pull it up before startup. 1.8 V power domain GNSS_RXD 28 DI GNSS UART receive 1.
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LPWA Module Series BG95 Series Hardware Design Figure 17: Main UART Reference Design (Translator Chip) Please visit http://www.ti.com/ for more information. Another example with transistor translation circuit is shown as below. For the design of circuits in dotted lines, see that of circuits in solid lines, but please pay attention to the direction of connection.
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LPWA Module Series BG95 Series Hardware Design Figure 19: Reference Circuit with Dual-Transistor Circuit (Recommended for GNSS UART) NOTE GNSS_TXD is a BOOT_CONFIG pin (pin 27), therefore voltage-level translation IC solution with pull-up circuit or signal transistor/MOSFET circuit is not applicable to it. The dual-transistor circuit solution is recommended for GNSS UART. 3.12.
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LPWA Module Series BG95 Series Hardware Design Table 17: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description Comment PCM_CLK 4 DO PCM clock 1.8 V power domain. PCM_SYNC 5 DO PCM data frame sync 1.8 V power domain. PCM_DIN 6 DI PCM data input 1.8 V power domain. PCM_DOUT 7 DO PCM data output 1.8 V power domain. I2C_SCL 40 OD I2C serial clock (for external codec) Require external pull-up to 1.8 V.
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LPWA Module Series BG95 Series Hardware Design Table 18: Pin Definition of NET_STATUS Pin Name Pin No. I/O Description Comment NET_STATUS 21 DO Module network activity status indication 1.
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LPWA Module Series BG95 Series Hardware Design Table 20: Pin Definition of STATUS Pin Name STATUS Pin No. 20 I/O Description Comment DO Module operation status indication 1.8 V power domain The following figure shows a reference circuit of STATUS. Figure 22: Reference Design of STATUS 3.15. Behaviors of MAIN_RI AT+QCFG="risignaltype","physical" command can be used to configure MAIN_RI pin behavior. No matter on which port the URC is presented, the URC will trigger the behavior of MAIN_RI pin.
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LPWA Module Series BG95 Series Hardware Design 2. “*” means under development. 3.16. USB_BOOT Interface BG95 provides a USB_BOOT pin. During development or factory production, USB_BOOT can force the module to boot from USB port for firmware upgrade. Table 22: Pin Definition of USB_BOOT Interface Pin Name USB_BOOT Pin No. 75 I/O Description Comment DI Force the module into emergency download mode 1.8 V power domain. Active high. If unused, keep it open.
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LPWA Module Series BG95 Series Hardware Design Figure 24: Timing of Turning on Module with USB_BOOT NOTES 1. It is recommended to reserve the above circuit design during application design. 2. Please make sure that VBAT is stable before pulling down PWRKEY. It is recommended that the time between powering up VBAT and pulling down PWRKEY is no less than 30 ms. 3. When using MCU to control the module entering emergency download mode, please follow the above timing sequence.
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LPWA Module Series BG95 Series Hardware Design Table 23: Pin Definition of ADC Interface Pin Name Pin No. I/O Description ADC0 24 AI General-purpose ADC interface ADC1 2 AI General-purpose ADC interface Comment Do not use ADC0 and ADC1 simultaneously. The following table describes the characteristics of ADC interfaces. Table 24: Characteristics of ADC Interfaces Parameter Min. Voltage Range 0.1 Typ. Max. Unit 1.8 V Resolution (LSB) 64.
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LPWA Module Series BG95 Series Hardware Design Table 25: Pin Definition of GPIO Interfaces Pin Name Pin No.
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LPWA Module Series BG95 Series Hardware Design 3.19. GRFC Interfaces The module provides two generic RF control interfaces for the control of external antenna tuners. Table 27: Pin Definition of GRFC Interfaces Pin Name Pin No. Description Comments GRFC1 83 Generic RF controller 1.8 V power domain. Generic RF controller BOOT_CONFIG. Do not pull it up before startup. 1.8 V power domain. GRFC2 84 Table 28: Logic Levels of GRFC Interfaces Parameter Min. Max. Unit VOL 0 0.45 V VOH 1.
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LPWA Module Series BG95 Series Hardware Design 4 GNSS Receiver 4.1. General Description BG95 includes a fully integrated global navigation satellite system solution that supports Gen9 VT of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). The module supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data update rate via USB interface by default. By default, BG95 GNSS engine is switched off. It has to be switched on via AT command.
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LPWA Module Series BG95 Series Hardware Design Hot start @ open sky Accuracy (GNSS) CEP-50 Autonomous 1.6 s XTRA enabled 1.5 s Autonomous @open sky <3 m NOTES 1. 2. 3. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously). Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 3 minutes after loss of lock.
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LPWA Module Series BG95 Series Hardware Design 5 Antenna Interfaces BG95 includes a main antenna interface and a GNSS antenna interface. The antenna ports have an impedance of 50 Ω. 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of main antenna interface is shown below. Table 31: Pin Definition of Main Antenna Interface Pin Name Pin No. I/O Description Comment ANT_MAIN 60 IO Main antenna interface 50 Ω characteristic impedance 5.1.2.
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LPWA Module Series BG95 Series Hardware Design LTE-FDD B13 777–787 746–756 MHz LTE-FDD B18 815–830 860–875 MHz LTE-FDD B19 830–845 875–890 MHz LTE-FDD B20 832–862 791–821 MHz LTE-FDD B25 1850–1915 1930–1995 MHz LTE-FDD B26 1) 814–849 859–894 MHz LTE-FDD B27 1) 807–824 852–869 MHz LTE-FDD B28 703–748 758–803 MHz LTE-FDD B31 3) 452.5–457.5 462.5–467.
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LPWA Module Series BG95 Series Hardware Design Figure 25: Reference Design of Main Antenna Interface 5.1.4. Reference Design of RF Layout For users’ PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, height from the reference ground to the signal layer (H), and the clearance between RF traces and grounds (S).
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LPWA Module Series BG95 Series Hardware Design Figure 27: Coplanar Waveguide Design on a 2-layer PCB Figure 28: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 29: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) BG95_Series_Hardware_Design 67 / 106
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LPWA Module Series BG95 Series Hardware Design In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:       Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground.
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LPWA Module Series BG95 Series Hardware Design A reference design of GNSS antenna interface is shown as below. Figure 30: Reference Circuit of GNSS Antenna Interface NOTES 1. 2. An external LDO can be selected to supply power according to the active antenna requirement. If the module is designed with a passive antenna, then the VDD circuit is not needed. 5.3. Wi-Fi Antenna Interface* BG95-MF supports Wi-Fi antenna interface through which the module realizes Wi-Fi positioning (receiving only).
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LPWA Module Series BG95 Series Hardware Design 5.4. Antenna Installation 5.4.1. Antenna Requirements The following table shows the requirements on main antenna and GNSS antenna. Table 36: Antenna Requirements Antenna Type Requirements GNSS 1) Frequency range: 1559–1609 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi Active antenna noise figure: < 1.
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LPWA Module Series BG95 Series Hardware Design Figure 31: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 32: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector.
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LPWA Module Series BG95 Series Hardware Design Figure 33: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com/.
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LPWA Module Series BG95 Series Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 37: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_BB -0.5 6.0 V VBAT_RF -0.3 6.0 V USB_VBUS -0.3 5.5 V Voltage at Digital Pins -0.3 2.09 V 6.2.
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LPWA Module Series BG95 Series Hardware Design IVBAT Peak supply current (during transmission slot) USB_VBUS USB detection Maximum power control level on EGSM900 BG95-M4 3.2 3.8 4.2 V BG95-MF TBD 3.8 TBD V BG95-M3/ BG95-M5 1.8 2.0 A BG95 series 5.0 V 6.3. Operating and Storage Temperatures The operating and storage temperatures of the module are listed in the following table. Table 39: Operating and Storage Temperatures Parameter Min. Typ. Max.
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LPWA Module Series BG95 Series Hardware Design Table 40: BG95-M1 Current Consumption (3.3 V Power Supply, Room Temperature) Description Conditions Average Max. Unit Leakage 1) Power-off @ USB and UART disconnected 14 - μA PSM 2) Power Saving Mode 4 - μA Rock Bottom AT+CFUN=0 @ Sleep mode 0.53 - mA LTE Cat M1 DRX = 1.28 s 1.7 - mA LTE Cat M1 e-I-DRX = 81.92 s @ PTW = 2.56 s, DRX = 1.28 s 0.577 - mA LTE Cat M1 DRX = 1.28 s 20 - mA LTE Cat M1 e-I-DRX = 81.92 s @ PTW = 2.
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LPWA Module Series BG95 Series Hardware Design Band 66 @ 20.65 dBm 193 418 mA Band 85 @ 21.01 dBm 208 458 mA Table 41: BG95-M2 Current Consumption (3.3 V Power Supply, Room Temperature) Description Conditions Average Max. Unit Leakage 1) Power-off @ USB and UART disconnected 14 - μA PSM 2) Power Saving Mode 3.9 - μA Rock Bottom AT+CFUN=0 @ Sleep mode 0.51 - mA LTE Cat M1 DRX = 1.28 s 1.7 - mA LTE Cat NB1 DRX = 1.28 s 1.6 - mA LTE Cat M1 e-I-DRX = 81.92 s @ PTW = 2.
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LPWA Module Series BG95 Series Hardware Design LTE Cat NB1 data transfer (GNSS OFF) Band 13 @ 21.31 dBm 227 533 mA Band 18 @ 21.09 dBm 216 498 mA Band 19 @ 21.21 dBm 219 508 mA Band 20 @ 21.21 dBm 218 501 mA Band 25 @ 21.1 dBm 202 455 mA Band 26 @ 21.28 dBm 219 508 mA Band 27 @ 21.08 dBm 217 502 mA Band 28A @ 21.27 dBm 213 477 mA Band 28B @ 21.05 dBm 215 497 mA Band 66 @ 20.76 dBm 190 407 mA Band 85 @ 21.06 dBm 205 457 mA Band 1 @ 21.
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LPWA Module Series BG95 Series Hardware Design Table 42: BG95-M3 Current Consumption (3.8 V Power Supply, Room Temperature) Description Conditions Average Max. Unit Leakage 1) Power-off @ USB and UART disconnected 14.5 - μA PSM 2) Power Saving Mode 3.9 - μA Rock Bottom AT+CFUN=0 @ Sleep mode 0.575 - mA LTE Cat M1 DRX = 1.28 s 1.65 - mA LTE Cat NB1 DRX = 1.28 s 1.56 - mA LTE Cat M1 e-I-DRX = 81.92 s @ PTW = 2.56 s, DRX = 1.28 s 0.63 - mA LTE Cat NB1 e-I-DRX = 81.
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LPWA Module Series BG95 Series Hardware Design LTE Cat NB1 data transfer (GNSS OFF) GPRS data transfer (GNSS OFF) Band 20 @ 20.94 dBm 192 429 mA Band 25 @ 20.09 dBm 186 416 mA Band 26 @ 21.19 dBm 193 436 mA Band 27 @ 21.12 dBm 193 437 mA Band 28A @ 20.99 dBm 188 431 mA Band 28B @ 20.97 dBm 190 425 mA Band 66 @ 20.95 dBm 181 382 mA Band 85 @ 21.06 dBm 185 405 mA Band 1 @ 21.19 dBm 149 373 mA Band 2 @ 21.43 dBm 151 384 mA Band 3 @ 21.4 dBm 144 360 mA Band 4 @ 21.
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LPWA Module Series BG95 Series Hardware Design EDGE data transfer (GNSS OFF) GPRS PCS1900 4UL/1DL @ 25 dBm 382 809 mA EDGE GSM850 4UL/1DL @ 23 dBm 523 1076 mA EDGE GSM900 4UL/1DL @ 21 dBm 496 1084 mA EDGE DCS1800 4UL/1DL @ 21 dBm 432 908 mA EDGE PCS1900 4UL/1DL @ 21 dBm 421 868 mA Table 43: BG95-M5 Current Consumption (3.8 V Power Supply, Room Temperature) Description Conditions Average Max.
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LPWA Module Series BG95 Series Hardware Design LTE Cat NB1 data transfer (GNSS OFF) Band 5 @ 23.49 dBm 231 563 mA Band 8 @ 22.99dBm 226 545 mA Band 12 @ 22.95 dBm 210 494 mA Band 13 @ 22.81 dBm 220 523 mA Band 18 @ 22.42 dBm 218 518 mA Band 19 @ 23.23 dBm 227 550 mA Band 20 @ 22.31 dBm 220 521 mA Band 25 @ 22.97 dBm 223 534 mA Band 26 @ 23.12 dBm 227 549 mA Band 27 @ 23.18 dBm 225 547 mA Band 28A @ 23.09 dBm 214 508 mA Band 28B @ 22.
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LPWA Module Series BG95 Series Hardware Design GPRS data transfer (GNSS OFF) EDGE data transfer (GNSS OFF) Band 66 @ 23.51 dBm 203 554 mA Band 71 @ 23.62 dBm 185 493 mA Band 85 @ 22.
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LPWA Module Series BG95 Series Hardware Design LTE Cat M1 data transfer (GNSS OFF) LTE Cat NB1 data transfer (GNSS OFF) LTE Cat NB1 e-I-DRX = 81.92 s @ PTW = 2.56 s, DRX = 1.28 s 14 - mA Band 1 @ 23.03 dBm 207 491 mA Band 2 @ 22.91 dBm 203 473 mA Band 3 @ 23.2dBm 211 499 mA Band 4 @ 23.18 dBm 211 500 mA Band 5 @ 23.02 dBm 213 505 mA Band 8 @ 23.47 dBm 231 563 mA Band 12 @ 23.08 dBm 195 444 mA Band 13 @ 23.04 dBm 204 473 mA Band 18 @ 23.
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LPWA Module Series BG95 Series Hardware Design Band 13 @ 23.06 dBm 169 443 mA Band 18 @ 23.32 dBm 184 486 mA Band 19 @ 23.26 dBm 188 493 mA Band 20 @ 23.31 dBm 183 480 mA Band 25 @ 23.27 dBm 171 458 mA Band 28 @ 23.6 dBm 167 432 mA Band 66 @ 23.12 dBm 179 474 mA Band 71 @ 23.11 dBm 157 412 mA Band 85 @ 23.13 dBm 160 409 mA NOTES 1.
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LPWA Module Series BG95 Series Hardware Design Tracking (AT+CFUN=0) Warm start @ Instrument 71 mA Lost start @ Instrument 69 mA Instrument Environment @ Passive Antenna 55 mA Table 47: GNSS Current Consumption of BG95-M5/-M6 (3.8 V Power Supply, Room Temperature) Description Searching (AT+CFUN=0) Tracking (AT+CFUN=0) Conditions Typ. Unit Cold start @ Instrument 68 mA Host start @ Instrument 67 mA Lost start @ Instrument 69 mA Instrument Environment @ Passive Antenna 53 mA 6.5.
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LPWA Module Series BG95 Series Hardware Design LTE-FDD B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/B20/ B25/B26 1)/B27 1)/B28/B66/B85 21 dBm +1.7/-3 dB < -39 dBm LTE-FDD B31/B72/B73 3) 23 dBm ±2 dB < -39 dBm Frequency Max. Min.
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LPWA Module Series BG95 Series Hardware Design LTE-FDD B4 -108/-102.3 LTE-FDD B5 -107.6/-100.8 LTE-FDD B8 -108/-99.8 LTE-FDD B12 -108.6/-99.3 LTE-FDD B13 -107/-99.3 LTE-FDD B18 -108/-102.3 LTE-FDD B19 -108/-102.3 LTE-FDD B20 -108/-99.8 LTE-FDD B25 -108.2/-100.3 LTE-FDD B26 -108.2/-100.3 LTE-FDD B27 -108.4-100.8 LTE-FDD B28 -106.8/-100.8 LTE-FDD B66 -107.8/-101.8 LTE-FDD B71 Not Supported LTE-FDD B85 -108.4/-99.
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LPWA Module Series BG95 Series Hardware Design LTE-FDD B12 -107/-99.3 -116/-107.5 LTE-FDD B13 -107/-99.3 -114/-107.5 LTE-FDD B18 -107/-102.3 -116/-107.5 LTE-FDD B19 -107/-102.3 -116/-107.5 LTE-FDD B20 -107/-99.8 -115/-107.5 LTE-FDD B25 -107/-100.3 -115/-107.5 LTE-FDD B26 -107/-100.3 Not Supported LTE-FDD B27 -107/-100.8 Not Supported LTE-FDD B28 -107/-100.8 -115/-107.5 LTE-FDD B66 -107/-101.8 -115/-107.5 LTE-FDD B71 Not Supported -115/-107.5 LTE-FDD B85 -107/-99.
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LPWA Module Series BG95 Series Hardware Design LTE-FDD B13 -106.5-99.3 -115/-107.5 LTE-FDD B18 -106/-102.3 -115/-107.5 LTE-FDD B19 -106/-102.3 -115/-107.5 LTE-FDD B20 -106/-99.8 -114/-107.5 LTE-FDD B25 -106/-100.3 -114/-107.5 LTE-FDD B26 -106/-100.3 Not Supported LTE-FDD B27 -106.5/-100.8 Not Supported LTE-FDD B28 -106/-100.8 -115/-107.5 LTE-FDD B66 -106.5-101.8 -114/-107.5 LTE-FDD B71 Not Supported -115/-107.5 LTE-FDD B85 -106.5/-99.3 -115/-107.
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LPWA Module Series BG95 Series Hardware Design LTE-FDD B13 -107.5/-99.3 -114/-107.5 LTE-FDD B18 -107.5/-102.3 -115/-107.5 LTE-FDD B19 -107.5/-102.3 -114/-107.5 LTE-FDD B20 -107.5/-99.8 -114/-107.5 LTE-FDD B25 -107.5/-100.3 -114/-107.5 LTE-FDD B26 -107.5/-100.3 Not Supported LTE-FDD B27 -107.5/-100.8 Not Supported LTE-FDD B28 -107.5/-100.8 -114/-107.5 LTE-FDD B66 -107.5/-101.8 -114/-107.5 LTE-FDD B71 Not Supported -115/-107.5 LTE-FDD B85 -107.5/-99.3 -114/-107.
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LPWA Module Series BG95 Series Hardware Design Table 55: Electrostatic Discharge Characteristics (25 ºC, 45 % Relative Humidity) Tested Interfaces Contact Discharge Air Discharge Unit VBAT, GND ±6 ±8 kV Main/GNSS Antenna Interfaces ±5 ±6 kV BG95_Series_Hardware_Design 91 / 106
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LPWA Module Series BG95 Series Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 7.1. Top and Side Dimensions 19.9±0.15 2.2±0.2 23.6±0.
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LPWA Module Series BG95 Series Hardware Design 19.90±0.15 1.00 1.10 0.25 1.95 1.10 0.55 1.00 Pin 1 5.10 0.25 23.60±0.15 8.50 1.00 0.85 1.70 1.90 1.10 1.00 1.70 1.00 1.70 0.70 0.50 0.25 0.55 0.25 1.10 40x1.0 62x0.7 40x1.0 62x1.10 Figure 35: Module Bottom Dimensions (Bottom View) NOTE The package warpage level of the module conforms to JEITA ED-7306 standard.
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LPWA Module Series BG95 Series Hardware Design 7.2. Recommended Footprint 19.90±0.15 9.95 9.15 7.45 1.00 9.95 9.15 7.15 1.95 1.10 0.55 1.10 0.25 1.00 0.25 2.50 Pin 1 1.70 1.70 1.10 0.85 1.70 1.70 2.55 0.85 1.00 1.10 1.00 11.80 11.00 9.60 7.65 5.95 4.25 0.25 0.20 1.90 0.15 1.70 23.60±0.15 0.85 11.80 11.00 9.70 7.65 5.95 4.25 1.70 0.70 1.10 2.50 1.10 1.10 0.25 4.25 5.95 4.25 5.95 40x1.0 62x0.7 62x1.10 40x1.0 Figure 36: Recommended Footprint (Top View) NOTES 1. 2. 3.
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LPWA Module Series BG95 Series Hardware Design 7.3. Bottom Views Figure 38: Bottom View of the Module NOTE These are renderings of BG95 module. For authentic appearance, see the module that you receive from Lantronix, Inc.l.
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LPWA Module Series BG95 Series Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage BG95 series module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35 % to 60 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3.
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LPWA Module Series BG95 Series Hardware Design NOTES 1. 1) This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. If the temperature and moisture do not conform to IPC/JEDEC J-STD-033 or the relative moisture is over 60 %, it is recommended to start the solder reflow process within 24 hours after the package is removed.
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LPWA Module Series BG95 Series Hardware Design Table 56: Recommended Thermal Profile Parameters Factor Recommendation Soak Zone Max slope 1–3 °C/s Soak time (between A and B: 150 °C and 200 °C) 70–120 s Reflow Zone Max slope 2–3 °C/s Reflow time (D: over 220 °C) 45–70 s Max temperature 238–246 °C Cooling down slope -1.5 to -3 °C/s Reflow Cycle Max reflow cycle 1 8.3. Packaging BG95 is packaged in a vacuum-sealed bag which is ESD protected.
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LPWA Module Series BG95 Series Hardware Design Figure 40: Tape Dimensions Figure 41: Reel Dimensions BG95_Series_Hardware_Design 99 / 106
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LPWA Module Series BG95 Series Hardware Design Table 57: Packaging Specifications of BG95 MOQ for MP Minimum Package: 250 Minimum Package × 4 = 1000 250 Size: 370 mm × 350 mm × 56 mm N.W: 0.61 kg G.W: 1.35 kg Size: 380 mm × 250 mm × 365 mm N.W: 2.45 kg G.W: 6.
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LPWA Module Series BG95 Series Hardware Design 9 Appendix A References Table 58: Related Documents Remark UMTS<E EVB user guide AT commands manual of BG95 series and BG77 modules GNSS application note of BG95 series, BG77 and BG600L-M3 modules RF layout application note Table 59: Terms and Abbreviations Abbreviation Description AMR Adaptive Multi-rate bps Bits Per Second CHAP Challenge Handshake Authentication Protocol CS Coding Scheme CTS Clear To Send DFOTA Delta Firmware Upgrade Over T
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LPWA Module Series BG95 Series Hardware Design EPC Evolved Packet Core ESD Electrostatic Discharge FDD Frequency Division Duplex FR Full Rate GMSK Gaussian Minimum Shift Keying GSM Global System for Mobile Communications HSS Home Subscriber Server I/O Input/Output Inorm Normal Current LED Light Emitting Diode LNA Low Noise Amplifier LTE Long Term Evolution MO Mobile Originated MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol PCB Print
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LPWA Module Series BG95 Series Hardware Design TDD Time Division Duplexing TX Transmitting Direction UL Uplink UE User Equipment URC Unsolicited Result Code (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Max
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LPWA Module Series BG95 Series Hardware Design 10 Appendix B GPRS Coding Schemes Table 60: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
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LPWA Module Series BG95 Series Hardware Design 11 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
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LPWA Module Series BG95 Series Hardware Design 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 BG95_Series_Hardware_Design 106 / 106
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LPWA Module Series BG95 Series Hardware Design 12 Appendix D EDGE Modulation and Coding Schemes Table 62: EDGE Modulation and Coding Schemes Coding Schemes Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot MCS-1 GMSK C 8.80 kbps 17.60 kbps 35.20 kbps MCS-2 GMSK B 11.2 kbps 22.4 kbps 44.8 kbps MCS-3 GMSK A 14.8 kbps 29.6 kbps 59.2 kbps MCS-4 GMSK C 17.6 kbps 35.2 kbps 70.4 kbps MCS-5 8-PSK B 22.4 kbps 44.8 kbps 89.6 kbps MCS-6 8-PSK A 29.6 kbps 59.2 kbps 118.
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LPWA Module Series BG95 Series Hardware Design 13 Appendix E Compulsory Certifications BG95_Series_Hardware_Design 108 / 106