Product Info

LP
WA Module Series
BG95 Series Hardware Design
BG95_S
eries_Hardware_Design 26 / 106
2.
2)
BG95-MF
does not support GPIO3 and GPIO4 interfaces (pin 64 and pin 65).
3.
3)
BG95-M4 does n
ot support GRFC interfaces (pin 83 and pin 84)
.
4. Do not use ADC0 and ADC1 simultaneously, as ADC1 connects directly to ADC0 inside the module.
BG95 s
eries module supports use of only one ADC interface at a time: either ADC0 or ADC1.
5. PWRKEY output voltage is 1.5 V because of the voltage drop inside the Qualcomm chipset. Due to
pl
atform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, never pu
ll
down
PWRKEY to GND permanently.
6. RES
ET_N connects directly to PWRKEY inside the module.
7. GNS
S_TXD (pin 27) and GRFC2 (pin 84) are BOOT_CONFIG pins. Never pull them up before
star
tup, otherwise the module cannot power on normally.
8. Kee
p all RESERVED pins and unused pins unconnected.
9. Co
nnect GND pins to the ground in the desi
gn.
3.2. Pin Desc
ription
The
following tables show the pin definition and description of BG95 series module.
Table 4: Definition of I/O Parameters
Ty
pe
De
scription
AI Ana
log Input
AO Ana
log Output
DI Digita
l Input
DO Digita
l Output
IO Bidire
ctional
PI Power Input
PO Power Out
put