Data Sheet

xPico
®
200 Series Embedded Wi-Fi
®
Gateway Data Sheet 24
controller peripheral block or a soft function. These pins are 3.3V CMOS logic level tolerant.
Table 4-5: xPico 200 Module GPIO Signal Definitions
Pin
Name
Description Reset State xPico 200
SMT Pin
Edge
Connector
Pin
CP1
Configurable I/O-USB Over Current Flag
Input
38
50
CP2/INT
Configurable I/O-SPI interrupt input-USB
Host Port Power Enable Output
Input
12
48
CP3
Configurable I/O-SPI MISO
1
Input
8
46
CP4
Configurable I/O-SPI MOSI
1
Input
9
44
CP5
Configurable I/O-I2C bus data
1
Input
15
58
CP6
Configurable I/O-I2C bus clock
1
Input
16
60
CP7
Configurable I/O-SPI Clock
1
Input
10
42
CP8
Configurable I/O-SPI Chip Select
1
Input
11
40
CP9
Configurable I/O-PWM
Input
22
16
CP10
Configurable I/O-PWM
Input
37
62
CP11
Configurable I/O
Input
40
68
CP12
Configurable I/O
Input
39
66
1
SPI/I2C Interfaces (SPI Master) are reserved for a future update. Contact your local sales
representative for availability.
System Pins
The xPico 200 module has three system pins:
♦ EXT_RESET# is the unit hardware reset, active low. Drive low for 50 ms to reboot unit.
Signal should be driven high or pulled high after reset. EXT_RESET# is inactive during
module power down (standby) state. Assert WAKE signal to come out of low power
states prior to asserting reset.
♦ DEFAULT# is the unit reset to default, active low. Drive low for 6 seconds or longer to
reset unit to default settings. May be left floating if unused.
♦ WAKE is the toggle signal to WAKE from the STANDBY state. WAKE signal is noise
sensitive. Filter as close as possible to the module pin.
See the xPico 200 Series Embedded Wi-Fi Gateway Integration Guide available at
https://www.lantronix.com/products/xpico-200/
for more details.