Data Sheet

Table Of Contents
xPico
®
200 Series Embedded Wi-Fi
®
Gateway Data Sheet 38
SPI Slave Timing
The diagram below shows the timing requirement for SPI_CLK, SPI_DIN, and SPI_DOUT. Data
is sampled on the rising edge of the clock.
Figure 8-4 SPI Slave Timing
Table 8-14: SPI Slave Timing
Parameter Description Minimum Maximum Unit
T1
Clock period. F
max
= 50 MHz.
2.08
-
ns
T2/T3
Clock high/low.
(0.45 x T1) T4
(0.55 x T1) T4
ns
T4/T5
Clock rise/fall time.
-
2.5
ns
T6
Input setup time, SIMO valid to SPI_CLK
active edge.
5.0 - ns
T7
Input hold time, SPI_CLK active edge to
SIMO invalid.
5.0 - ns
T8
Output setup time, SOMI valid before
SPI_CLK rising.
5.0 - ns
T9
Output hold time, SPI_CLK active edge to
SOMI invalid.
5.0 - ns
CSX to clock
CSX fall to 1
st
rising edge. SPI_CSx
remains active for the entire duration of SPI
Slave read/write/write_read transaction.
7.86 - ns
Clock to CSX
Last falling edge to CSX high.
-
-
ns