Data Sheet

xPico
®
200 Series Embedded Wi-Fi
®
Gateway Data Sheet 39
SPI Master Timing
The diagram below shows the timing requirement for CS, CK, SDI, and SDO.
Figure 8-5 SPI Master Timing
Table 8-15: SPI Master Timing
Parameter Description Minimum Maximum Unit
Operating Voltage
VDDIO
V
Frequency of operation
1
26.7
MHz
T1
SCK output cycle time
1/26.7MHz
ns
T2
SCK output high/low time
18
ns
T3
CS Active to SCK delay
880
ns
T4
SCK to CS inactive delay
756
ns
T5
SCK to MOSI valid
-
13
ns
T6
SCK to MOSI invalid
35.6
ns