User Manual

3. SRF 3943-2 RF Power Amplifier: Figures 3, 4, 5, 7, 8, and 9.
The Power Amplifier (PA) is configured in push-pull, using dual N-channel
enhancement mode Field Effect RF power transistors which are packaged into a
single case and operated in class AB.
The Low Band and High Band versions of the PA differ slightly due to the
frequency ranges to be covered.
3.1 Low Band PA Circuit Description (30C1054 input board, 30C1055 output board)
The PA consists of two, source grounded N-channel, insulated gate Field Effect
Transistors (FETs) packaged in a single case, operating class AB in a push-pull
configuration. The original schematic indicates a type MRF-151-G as the dual FET
used; we now use a "selected MRF-151-G to tightly controlled specifications"
which is proprietary to LARCAN and designated type SRF 3943-2. This selection
simply tightens the gain specification for operation in High Band, and in case of
emergency, there is no reason an MRF-151-G could not be substituted for Low Band
operation.
Because these FETs are "enhancement mode N-channel" devices, they require
positive gate-to-source bias voltage on each gate to cause source-drain
conduction. The quiescent Class AB idling bias current is set at 0.6 ampere for
each half. The gate voltage required to produce this idling current may vary
between 2 V and 5 V according to the device specification sheet, and typically is
3 to 4 V. FET gate threshold voltages also are temperature sensitive, so thermal
compensation is provided by RT1 and RT2.
Gate bias is supplied out of adjustable voltage dividers from +20 V regulated
bias sources CR1 and CR2. Current limiting to these zener diodes is provided
through R1 and R8. Resistors R9, R2, R3, R4, and RT1 provide gate bias for the
"A" half of the amplifier; R10, R7, R6, R5, and RT2 provide bias for the "B"
half.
The RF input signal arriving in J1 is applied to balun T1 to provide two signals
180° out-of-phase. These antiphase signals are stepped down to match the low
input impedance of the FET through a ð-network consisting of C1, C2, C3, L1, L2,
C4, and the device input capacitance, and then applied to the gates. The
capacitance value of C4 is changed for operation on channels 5 & 6. The gate
input impedance at the operating frequency is low compared with the values of R3
and R6, which have little or no effect at RF.
R3 and R6 provide a DC path for bias, and provide loading at lower frequencies
where gate impedance is high, in order to assist in maintaining amplifier
stability. The choice of C6, C7, C20, and C21 values, their series inductances,
and that of board traces, also ensures effective bypassing at critical
frequencies.
The output matching ð-network, consisting of inductors L3 thru L8, and
capacitances C13 thru C16, transforms the very low output impedance of the FET,
upwards to a standard 50 Ù. The two antiphase output signals are finally
combined in balun T2, L9. Jumpers placed across parts of L7 and L8, plus the
changed values of C13, C14, C15 and C16, configures the system for channels 5 & 6