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LeddarVu User Guide Page 48 of 129
The status register and bit flags are presented in Table 16.
Table 16: Status register
Bit
Name
Access
Description
7:2
Reserved
R/W
Future use
1
Write enable
latch
R
0 = Write disabled
1 = Write enabled
0
Module ready
R
0 = Module ready
1 = Module busy (programming, erasing)
Data chronograms are represented in Figure 22 and Figure 23, and opcode and register
chronograms are presented in Figure 24 and Figure 25 below.