User Manual

Thermal Specifications
148 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
7.3.2.6.9 T-state Throttling Control Read / Write
PECI offers the ability to enable and configure ACPI T-state (core clock modulation)
throttling. ACPI T-state throttling forces all CPU cores into duty cycle clock modulation
where the core toggles between C0 (clocks on) and C1 (clocks off) states at the
specified duty cycle. This throttling reduces CPU performance to the duty cycle
specified and, more importantly, results in processor power reduction.
The processor supports software initiated T-state throttling and automatic T-state
throttling as part of the internal Thermal Monitor response mechanism (upon TCC
activation). The PECI T-state throttling control register read/write capability is
managed only in the PECI domain. In-band software may not manipulate or read the
PECI T-state control setting. In the event that multiple agents are requesting T-state
throttling simultaneously, the CPU always gives priority to the lowest power setting, or
the numerically lowest duty cycle.
The only supported duty cycle is 12.5% (12.5% clocks on, 87.5% clocks off). It is
expected that T-state throttling will be engaged only under emergency thermal or
power conditions. Future products may support more duty cycles, as defined in the
following table:
Table 7-28. ACPI T-state Duty Cycle Definition
5 6 MC5_MISC[31:0]
5 7 MC3_MISC[63:32]
6 0 MC6_CTL[31:0]
6 1 MC6_CTL[63:32]
6 2 MC6_STATUS[31:0]
6 3 MC6_STATUS[63:32]
6 4 MC6_ADDR[31:0]
6 5 MC6_ADDR[63:32]
6 6 MC6_MISC[31:0]
6 7 MC6_MISC[63:32]
8 0 MC8_CTL[31:0]
8 1 MC8_CTL[63:32]
8 2 MC8_STATUS[31:0]
8 3 MC8_STATUS[63:32]
8 4 MC8_ADDR[31:0]
8 5 MC8_ADDR[63:32]
8 6 MC8_MISC[31:0]
8 7 MC8_MISC[63:32]
Table 7-27. Machine Check Bank Definitions (Sheet 3 of 3)
Bank Number Bank Index Meaning
Duty Cycle Code Definition
0x0 Undefined
0x1 12.5% clocks on / 87.5% clocks off
0x2 25% clocks on / 75% clocks off
0x3 37.5% clocks on / 62.5% clocks off