User Manual

Intel

Xeon

Processor 5600 Series Datasheet Volume 1 19

Electrical Specifications

Clock multiplying within the processor is provided by the internal phase locked loop

(PLL), which requires a constant frequency BCLK_DP, BCLK_DN input, with exceptions

for spread spectrum clocking. DC specifications for the BCLK_DP, BCLK_DN inputs are

provided in Table 2-14 and AC specifications in Table 2-22. These specifications must

be met while also meeting the associated signal quality specifications outlined in

Section 3.

2.1.6 Test Access Port (TAP) Signals

Due to the voltage levels supported by other components in the Test Access Port (TAP)

logic, it is recommended that the processor(s) be first in the TAP chain and followed by

any other components within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of

accepting an input of the appropriate voltage. Similar considerations must be made for

TCK, TDO, TMS, and TRST#. Two copies of each signal may be required with each

driving a different voltage level.

Processor TAP signal DC specifications can be found in Table 2-18. AC specifications are

located in Table 2-27.

Note: While TDI, TMS and TRST# do not include On-Die Termination (ODT), these signals are

weakly pulled-up via a 1-5 k resistor to V

Note: While TCK does not include ODT, this signal is weakly pulled-down via a

1-5 k resistor to V