User Manual

Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1 27
Electrical Specifications
2.1.7.4 Processor V
TT
Voltage Identification (VTT_VID) Signals
The voltage set by the VTT_VID signals is the typical reference voltage regulator (VR)
output to be delivered to the processor V
TTA
and V
TTD
lands. It is expected that one
regulator will supply all V
TTA
and V
TTD
lands. VTT_VID signals are CMOS push/pull
outputs. Please refer to Table 2-18 for the DC specifications for these signals.
Individual processor VTT_VID values may be calibrated during manufacturing such that
two devices at the same core frequency may have different default VTT_VID settings.
The processor utilizes three voltage identification signals to support automatic selection
of power supply voltages. These correspond to VTT_VID[4:2]. The V
TT
voltage level
delivered to the processor lands must also encompass a 20 mV offset (See Table 2-4;
V
TT_TYP
) above the voltage level corresponding to the state of the VTT_VID[7:0] signals
(See Table 2-4; VR 11.0 Voltage). Table 2-11 and Figure 2-10 provide the resulting
static and transient tolerances. Please note that the maximum and minimum electrical
loadlines are defined by a 31.5 mV tolerance band above and below V
TT_TYP
values.
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
2.1.8 Reserved or Unused Signals
All Reserved (RSVD) signals must remain unconnected. Connection of these signals to
V
CC
, V
TTA
, V
TTD
, V
DDQ
, V
SS
, or any other signal (including each other) can result in
component malfunction or incompatibility with future processors. See Section 5 for the
land listing and the location of all Reserved signals.
For reliable operation, connect unused inputs or bidirectional signals to an appropriate
signal level. Unused Intel QuickPath Interconnect input and output pins can be left
floating. Unused active high inputs should be connected through a resistor to ground
(V
SS
). Unused outputs can be left unconnected; however, this may interfere with some
TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, including a resistor will also allow for system testability.
Resistor values should be within ± 20% of the impedance of the baseboard trace,
unless otherwise noted in the appropriate platform design guidelines.
TAP signals do not include on-die termination, however they may include resistors on
package (refer to Section 2.1.6 for details). Inputs and utilized outputs must be
terminated on the baseboard. Unused outputs may be terminated on the baseboard or
left unconnected. Note that leaving unused outputs unterminated may interfere with
some TAP functions, complicate debug probing, and prevent boundary scan testing.
Table 2-4. V
TT
Voltage Identification Definition
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VR 11.0
Voltage
V
TT_TYP
(Voltage + Offset)
010
0 0 0 1 0 1.200V 1.220V
010
0 0 1 1 0 1.175V 1.195V
010
0 1 0 1 0 1.150V 1.170V
010
0 1 1 1 0 1.125V 1.145V
010
1 0 0 1 0 1.100V 1.120V
010
1 0 1 1 0 1.075V 1.095V
010
1 1 0 1 0 1.050V 1.070V
010
1 1 1 1 0 1.025V 1.045V