User Manual

Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1 47
Electrical Specifications
2.7 Intel® QuickPath Interconnect Specifications
Intel

QuickPath Interconnect specifications are defined at the processor
pins. In most cases, termination resistors are not required as these are integrated into
the processor silicon (Refer to Table 2-6).
Table 2-19. Common Intel® QuickPath Interconnect Specifications
Symbol Parameter Min Nom Max Unit Notes
UIavg Avg UI size at “f” GT/s
(f = 4.8, 5.86, or 6.4)
0.999 *
Nom
1000/f 1.001 *
Nom
psec
T
slew-rise-fall-pin
Defined as the slope of the rising or
falling waveform as measured between
+/- 100 mV of the differential transmitter
output, for any data or clock.
10 25 V / nsec
Z
TX_LOW_CM_DC
DC resistance of Tx terminations at half
the single ended swing (usually
0.25*V
Tx-diff-pp-pin
) bias point
38 52 
Z
TX_LOW_CM_DC
Defined as: (max(Z
TX_LOW_CM_DC
) -
min(Z
TX_LOW_CM_DC
)) / Z
TX_LOW_CM_DC
expressed in %, over full range of Tx
single ended voltage
-6 0 6 % of
Z
TX_LOW_CM_DC
Z
RX_LOW_CM_DC
DC resistance of Rx terminations at half
the single ended swing (usually
0.25*V
Tx-diff-pp-pin
) bias point
38 52 
Z
RX_LOW_CM_DC
Defined as: (max(Z
RX_LOW_CM_DC
) -
min(Z
RX_LOW_CM_DC
)) / Z
RX_LOW_CM_DC
expressed in %, over full range of Rx
single ended voltage
-6 0 6 % of
Z
RX_LOW_CM_DC
N
MIN-UI-Validation
# of UI over which the eye mask voltage
and timing spec needs to be validated
1,000,000 UI
Z
TX_HIGH_CM_DC
Single ended DC impedance to GND for
either D+ or D- of any data bit at Tx
10k  1
Z
RX_HIGH_CM_DC
Single ended DC impedance to GND for
either D+ or D- of any data bit at Rx
10k  2
Z
TX_LINK_DETECT
Link Detection Resistor 500 2000 
V
TX_LINK_DETECT
Link Detection Resistor Pull-up Voltage 1.6 V
T
DATA_TERM_SKEW
Skew between first to last data
termination meeting Z
RX_LOW_CM_DC
128 UI
T
INBAND_RESET_SENSE
Time taken by inband reset detector to
sense Inband Reset
1.5 µs
T
CLK_DET
Time taken by clock detector to observe
clock stability
20k UI
T
CLK_FREQ_DET
Time taken by clock frequency detector
to decide slow vs. operational clock after
stable clock
32 Reference
Clock Cycles
T
Refclk-Tx-Variability
Phase variability between Reference Clk
(at Tx input) and Tx output
500 psec
T
Refclk-jitter-rms-onepll
Accumulated rms jitter over n UI of a
given PLL model output in response to
the jittery reference clock input. The PLL
output is generated by convolving the
measured reference clock phase jitter
with a given PLL transfer function. Here
n=12.
0.5 psec
BER
Lane
Bit Error Rate per lane valid for 4.8, 5.86
and 6.4 GT/s
1.0E-14 Events
QPI[1,0]_COMP COMP Resistance 21.0-1% 21.0 21.0+1% 