User Manual

Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1 53
Electrical Specifications
6. The system memory clock outputs are differential (CLK and CLK#), the CLK rising edge is referenced at the
crossing point where CLK is rising and CLK# is falling.
7. The system memory strobe outputs are differential (DQS and DQS#), the DQS rising edge is referenced at
the crossing point where DQS is rising and DQS# is falling, and the DQS falling edge is referenced at the
crossing point where DQS is falling and DQS# is rising.
8. This values specifies the parameter after write leveling, representing the residual error in the controller
afrter training, and does not include any effects from the DRAM itself.
Table 2-25. DDR3/DDR3L Electrical Characteristics and AC Specifications at 1333 MT/s
(Sheet 1 of 2)
Symbol Parameter
Channel 0
Channel 1
Channel 2
Unit Figure Note
Max Min
System Memory Latency Timings
tCL – tRCD – tRP CAS Latency – RAS to CAS Delay –
Pre-charge Command Period
8 - 8 - 8
9 - 9 - 9
tCK
Electrical Characteristics
T
SLR_D
DQ[63:0], DQS_N[17:0],
DQS_P[17:0], ECC[7:0], MA[15:0]
Input Slew Rate
4.0 1.0 V/ns 2
System Memory Clock Timings
T
CK
CLK Period <1.875 1.50 ns
T
CH
CLK High Time 0.94 0.75 ns
T
CL
CLK Low Time 0.94 0.75 ns
T
SKEW
Skew Between Any System
Memory Differential Clock Pair
(CLK_P/CLK_N)
+155 ps
System Memory Command Signal Timings
T
CMD_CO
RAS#, CAS#, WE#, MA[15:0],
BA[2:0] Edge placement accuracy
+250 -250 ps 2-22 3,4,6
System Memory Control Signal Timings
T
CTRL_CS
CS#[7:0], CKE[3:0], ODT[3:0]
Edge placement accuracy
+250 -250 ps 2-22 3,6
System Memory Data and Strobe Signal Timings
T
DVA
+ T
DVB
DQ[63:0] Valid before and after
DQS[17:0] Rising or Falling Edge
0.67 * UI UI 7
T
SU
+ T
HD
DQ Input Setup plus Hold Time to
DQS Rising or Falling Edge
0.25 * UI ns 1,2,7
T
DQS_CO
DQS Edge Placement Accuracy to
CK Rising Edge BEFORE write
leveling
+250 -250 ns 2-24 3,6,7
T
DQS_CO
DQS Edge Placement Accuracy to
CK Rising Edge AFTER write
leveling
+165 -165 ns 2-24 3,6,7,8