User Manual

Electrical Specifications
64 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
Figure 2-28. Voltage Sequence Timing Requirements
VTTPWRGOOD
V
TT
BCLK
VCCPWRGOOD
VCC VID[7:0]
V
CC
V
DDQ
VDDPWRGOOD
RESET#
V
CCPLL
LFM VID From CPU
V
CCBOOT
Tk
Tj
POC
MSI D
V
LFM
Th
VTT VID FINAL
VTT_VID[2:0]
V
TTBOOT
V
TTSAFE
VTT VID from
VID Buffer
V
TTFINAL
Tb
Tm
Td
VDDPWRGOOD must assert before or at the same time as VCCPWRGOOD assertion
VTT must be stable before VCCPWRGOOD assertion
Varies based on BIOS execution
Dynamic VID From CPU
Tf
Refer to VRD11.1 specification for details on Vcc ramp timings
Ti
Te