Datasheet

Features
122 Intel® Xeon® Processor 7400 Series Datasheet
7.4.3.3.2 FSB: Front Side Bus Speed
This location contains the front side bus transaction rate information. Systems may
need to read this offset to decide if all installed processors support the same front side
bus speed. Because FSB is described as a 4X data bus, the transaction rate given in this
field is currently 1066 MTS. The data provided is the speed, rounded to a whole
number, and reflected in hex. Writes to this register have no effect.
Example: The Intel® Xeon® Processor 7400 Series supports a 1066 MTS front side
bus. Therefore, offset 1A - 1Bh has a value of 042Ah.
7.4.3.3.3 MPSUP: Multiprocessor Support
This location contains 2 bits for representing the supported number of physical
processors on the bus. These two bits are MSB aligned where 00b equates to single-
processor operation, 01b is a dual-processor operation, and 11b represents multi-
processor operation. The Intel® Xeon® Processor 7400 Series is an MP processor. The
remaining six bits in this field are reserved for the future use. Writes to this register
have no effect.
Example: The Intel® Xeon® Processor 7400 Series will use C0h at offset 1Ch.
7.4.3.3.4 MCF: Maximum Core Frequency
This location contains the maximum core frequency for the processor. The frequency
should equate to the markings on the processor and/or the S-spec speed even if the
parts are not limited or locked to the intended speed. Format of this field is in MHz,
rounded to a whole number, and encoded in hex format. Writes to this register have no
effect.
Example: A 2.93 GHz processor will have a value of 0675h, which equates to 2933
decimal. Therefore, offset 1D - 1Eh has a value of 0765h.
Offset: 1Ah-1Bh
Bit Description
15:0 Front Side Bus Speed
0000h-FFFFh: MTS
Offset: 1Ch
Bit Description
7:6 Multiprocessor Support
UP, DP or MP indictor
00b: UP
01b: DP
10b: Reserved
11b: MP
5:0 RESERVED
000000b-111111b: Reserved