Datasheet

Electrical Specifications
44 Intel® Xeon® Processor 7400 Series Datasheet
Figure 2-13. FSB Source Synchronous 2X (Address) Timing Waveform
T
p
/4 T
p
/2 3T
p
/4
BCLK0
BCLK1
ADSTB# (@ driver)
A# (@ driver)
A# (@
receiver)
ADSTB# (@ receiver)
valid valid
valid
valid
T
M
T
N
T
K
T
S
T
H
T
J
T
H
T
J
T
H
= T23: Source Sync. Address Output Valid Before Address Strobe
T
J
= T24: Source Sync. Address Output Valid After Address Strobe
T
K
= T27: Source Sync. Address Strobe Setup Time to BCLK
T
M
= T25: Source Sync. Input Setup Time
T
N
= T26: Source Sync. Input Hold Time
T
S
= T20: Source Sync. Output Valid Delay
T
P
= T1: BCLK[1:0] Period
T
R
T
R
= T31: Address Strobe Output Valid Delay
T0
T1
T2