User's Guide
Table Of Contents
- Document related firmware and hardware
- Form factor
- General Specifications
- Interfaces
- Specifications
- Regulatory conformity summary
- Technical Drawing
- GPIOs
- 16 pins connector
- 8 pins connector
- Power supply design
- Board layout
- Antenna performance
- Introduction
- Generic message structure
- Communication protocol
- Encryption (6 bits)
- Message Type (1 bit)
- Simplified Mode
- Message types
- Payload: Simplified Message type
- Message Type advanced
- Encryption Types
- Payload
- Payload [0] PayloadType <4: 0>
- payload [0] PayloadType <7: 5>
- TypeID
- Refresh
- DataWithoutAck
- DataWithAck
- FileTransfer
- Event
- Return
- Get
- Set
- Payload [1]: sub-type <7: 0>
- AckData 0x03
- RoutingTableInfo 0x20
- TableLvl1 0x21
- DebugInfos 0x22
- Settings 0x23
- Rssi 0x24
- MasterID 0x25
- NackInfos 0x2B
- DecryptionError 0x2C
- WrongParameter 0x2D
- Payload [1]: subType <7: 0>
- TypeID 0x00
- Refresh 0x01
- RoutingTableInfo 0x20
- TableLvl1 0x21
- DebugInfos 0x22
- Settings 0x23
- Rssi 0x24
- MasterID 0x25
- 0x23Settings
- MasterID 0x25
- ForceRelay 0x26
- Password 0x26
- ResetMcu 0x28
- CloseDevice 0x29
- United States (FCC)
- OEM labeling requirements
- FCC notices
- FCC-approved antennas
- RF exposure
- CANADA - ISED (Innovation, Science and Economic Development Canada)
- Labeling requirements
- Detachable antenna
- EUROPE (CE)
- Maximum power and frequency specifications
- OEM labeling requirements
- Declarations of conformity
- Antennas
12
8 pins connector"
Pins
Name
Type
Description
1
nMCLR
I
Master reset not (reset emMeah with 0V)
2
3.3V
P
3.3V output (max 200mA)
3
GND
P
Ground reference for logic and I/O pins
4
PGD
I/O
Programmation interface&
I/O pin (0-3.3V)
5
PGC
I/O
Programmation interface&
I/O pin (0-3.3V)
6
GND
P
Ground reference for logic and I/O pins
7
PWM1
O
Status LED control pin
8
nCHG
O
0V when charging(open drain)