Updated File Title 2 3 4 V1.0 Type LEO2-B Platform Hardware Manual 1 Rev. LEO2 Platform Hardware Manual 2008-09-08 Manual ABSTRACT This document is hardware manual for LEO2-B Platform board. Contents of this document are descriptions of each blocks and usage directions. It is recommended to peruse this manual before operating LEO2-B Platform 5 6 7 HISTORY Rev Status Date Author Contents 8 9 KEY WORDS 10 11 Mobile Communication Technology Research Lab.
Updated File 2008-09-08 Rev. LEO2 Platform Hardware Manual V1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 [Notice] 1. The product described in this manual may be modified without prior notice for reliability, functionality or design improvement. 2.
Updated File 2008-09-08 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1. 1.1 1.2 1.3 1.4 2. 2.1 2.2 2.3 2.4 3. 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4. 4.1 4.2 4.3 5. 6. Rev. LEO2 Platform Hardware Manual V1.0 CONTENTS Introduction............................................................................................................................... １ Scope ........................................................................................................................
Updated File 2008-09-08 Rev. LEO2 Platform Hardware Manual V1.0 1 2 3 4 5 6 7 8 9 10 11 12 FIGURES Figure 1. Photograph of LEO2-B platform ........................................................................................ ２ Figure 2. Top level block diagram .................................................................................................... ３ Figure 3. Placement map of LEO2-B .............................................................................................
Updated File 2008-09-08 Rev. LEO2 Platform Hardware Manual V1.0 1 2 3 4 TABLES Table 1. ARM processor setting DIP switches............................................................................... １０ Table 2. LED signal mapping........................................................................................................ １１ 5 6 LGE Proprietary v MCTR Lab.
Updated File 2008-09-08 1 1. Rev. LEO2 Platform Hardware Manual V1.0 Introduction 2 3 4 5 1.1 Scope This document intends to describe the brief architecture and usage of the LEO2-B Platform board. LEO2-B Platform board is designed for LTE User Equipment test and verification. 6 7 8 1.
Updated File 2008-09-08 1 2. Rev. LEO2 Platform Hardware Manual V1.0 Features and top level diagram 2 3 2.1 Features - ARM926EJ-S (max 333MHz) - AMBA 2.0 (max 166MHz) - 7 Virtex4 FX140 FPGA for Modem algorithm - RF interface (2 Receivers and 1 Transmitter) - Application interface - 512Mb DDR SDRAM, 1Gb NAND Flash - USB 2.0 High speed device - 100 Ethernet port - 1 Serial ports (up to 115 K baud) - JTAG and ETM Debug port 2.
Updated File 2008-09-08 1 2.3 Rev. LEO2 Platform Hardware Manual V1.
Updated File 2008-09-08 Rev. LEO2 Platform Hardware Manual V1.0 1 2 3. Block description 3 4 5 6 7 8 9 10 11 3.1 FPGA subsystem The LEO2-B Platform supports 7 FPGAs (xilinx virtex4 FX140, 1517pin package) for LTE UE modem algorithm.
Updated File 2008-09-08 1 2 Rev. LEO2 Platform Hardware Manual V1.0 The ARM processor is used to control the LTE UE modem logic. The processor has ARM926EJ-S core and peripheral controllers. 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ARM Processor - ARM926EJ-S core max. 333MHz, 16KB-I/D cache, configurable TMC-I/D size, MMU, TLB, JTAG and ETM trace module (multiplexed interfaces). - 32KByte Rom (code customizable) 8KByte common SRAM. - High performance linked list 8 channels DMA.
Updated File 2008-09-08 Rev. LEO2 Platform Hardware Manual V1.0 1 2 3.4 RF Interface 3 4 5 Figure 5. RF interface on LEO2-B platform board 6 7 8 9 Figure 6. Block diagram of RF daughter board 10 LGE Proprietary ６ MCTR Lab.
Updated File 2008-09-08 1 2 3 4 5 6 Rev. LEO2 Platform Hardware Manual V1.0 The LEO2-B Platform supports RF daughter board interface to verify and test LTE UE modem algorithm. The baseband IQ signals are transmitted and received on FPGAs, Transmit part is on TX FPGA and Receive part is on SRCH, MISO FPGA. The bit resolution of IQ signal is 12bits. The sampling frequencies are 122.88MHz for DAC and 61.44MHz for ADC.
Updated File 2008-09-08 Rev. LEO2 Platform Hardware Manual V1.0 1 2 3.6 Reset 3 4 5 Figure 8. Block diagram of platform board reset scheme 6 7 8 The reset CPLD manages whole system reset scheme for ARM, Ethernet transceiver and each FPGA reset. In the lower left lower corner of the platform board, a manual reset switch is provided. 9 10 11 3.7 Application interface 12 13 14 Figure 9.
Updated File 2008-09-08 Rev. LEO2 Platform Hardware Manual V1.0 1 2 3.8 Power Supplies 3 4 5 Figure 10. Block diagram of power supplies 6 7 8 9 External power supplied from DC input jack on the platform board. To proper operation, external AC to DC power supply should be 12V and >5A. All needed power sources of platform board are supplied from DC-DC converters and LDOs devices. 10 11 12 4. DIP switch, LED and logic probing connector 13 14 15 16 17 4.
Updated File 2008-09-08 Rev. LEO2 Platform Hardware Manual "off" : high signal to CPLD V1.0 1 6 DIPSW_CPLD(1) 7 SSP2_SS1 8 SMI_WE Pin No.
Updated File 2008-09-08 Rev. LEO2 Platform Hardware Manual LED49 SRCH GPIO(0) LED50 TX GPIO(0) LED51 SRCH GPIO(1) LED52 TX GPIO(1) LED53 SRCH GPIO(2) LED54 TX GPIO(2) LED55 SRCH GPIO(3) LED56 TX GPIO(3) LED57 RF power OK V1.0 Table 2. LED signal mapping 1 2 3 4 4.3 Logic probing connector 5 6 7 8 All of the logic analyzer probing headers are MICTOR connector type, agilent E5346A logic analyzer probing adaptor is needed to signal monitoring.
Updated File 2008-09-08 1 Rev. LEO2 Platform Hardware Manual V1.0 6. Reference [1] 2 3 4 5 Notice 6 7 OEM integrators and installers are instructed that the phrase. This device contains 8 Warning: Exposure to Radio Frequency Radiation The radiated output power of this device is far below the FCC radio frequency exposure limits. Nevertheless, the device should be used in such a manner that the potential for human contact during normal operation is minimized.
