User's Manual

LS5B User Manual
Libre Wireless Technologies User Manual: LS5B, Ver. 1.0 Page 81 of 89
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15. Design Requirement
Boot strap signals as mentioned in the Table 7-1, should not be driven by external devices
until the module (SoC) comes out of reset.
This mandates implementation of appropriate power sequencing mechanism
on base-board. That is, there has to be 150ms delay between Supplying power
to LS module (SoC) and power to any other device on the base-board.
Table 7-1: Boot Strap Signal Requirement
Typically 150 ms is the time taken to come out of the reset after power on of the module
(SoC).
Boot Strap Signal
Description
UART_TXD0
Can be driven logic low but should not be driven logic high.
UART_TXD1
Can be driven logic high but should not be driven logic low.
GPIO36
Can be driven logic high but should not be driven logic low.
I2S_TXD
Can be driven logic low but should not be driven logic high.