Datasheet

LTC2302/LTC2306
11
23026fa
BLOCK DIAGRAM
TEST CIRCUITS
TIMING DIAGRAMS
Voltage Waveforms for SDO Delay Times, t
dDO
and t
hDO
Voltage Waveforms for t
dis
Load Circuit for t
dis
Waveform 1 Load Circuit for t
dis
Waveform 2, t
en
SDI
SDO
SCK
CONVST
23026 BD
SERIAL
PORT
ANALOG
INPUT
MUX
CH0 (IN
+
)
CH1 (IN
–
)
V
REF
LTC2302
LTC2306
PIN NAMES IN PARENTHESIS
REFER TO LTC2302
V
DD
OV
DD
GND
12-BIT
500ksps
ADC
+
–
SDO TEST POINT
V
DD
3k
C
L
23026 TC01
SDO TEST POINT
3k
C
L
23026 TC02
SCK
SDO
V
IL
t
dDO
t
hDO
V
OH
V
OL
23026 TD01
SDO
WAVEFORM 1
(SEE NOTE 1)
V
IH
t
dis
90%
10%
SDO
WAVEFORM 2
(SEE NOTE 2)
CONVST
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
23026 TD02