Datasheet

LTC2302/LTC2306
12
23026fa
TIMING DIAGRAMS
t
WLCLK
(SCK Low Time)
t
WHCLK
(SCK High Time)
t
HD
(Hold Time SDI After SCK↑)
t
SUDI
(Setup Time SDI Stable Before SCK↑)
Voltage Waveforms for t
en
Voltage Waveforms for SDO Rise and Fall Times t
r
, t
f
APPLICATIONS INFORMATION
23026 TD03
SCK
SDI
t
WLCLK
t
WHCLK
t
HD
t
SUDI
23026 TD04
CONVST
SDO
t
en
SDO
t
r
t
f
23004 TD05
V
OH
V
OL
Overview
The LTC2302/LTC2306 are low noise, 500ksps, 1-/2-
channel, 12-bit successive approximation register (SAR)
A/D converters. The LTC2306 includes a 2-channel analog
input multiplexer (MUX) while the LTC2302 includes an
input MUX that allows the polarity of the differential input
to be selected. Both ADCs include an SPI-compatible
serial port for easy data transfers and can operate in
either unipolar or bipolar mode. Unipolar mode should be
used for single-ended operation with the LTC2306, since
single-ended input signals are always referenced to GND.
The LTC2302/LTC2306 can be put into a power-down sleep
mode during idle periods to save power.
Conversions are initiated by a rising edge on the CONVST
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, a 6-bit input word (D
IN
)
at the SDI input confi gures the MUX and programs vari-
ous modes of operation. As the D
IN
bits are shifted in,
data from the previous conversion is shifted out on SDO.
After the 6 bits of the D
IN
word have been shifted in, the
ADC begins acquiring the analog input in preparation for
the next conversion as the rest of the data is shifted out.
The acquire phase requires a minimum time of 240ns
for the sample-and-hold capacitors to acquire the analog
input signal.
During the conversion, the internal 12-bit capacitive
charge-redistribution DAC output is sequenced through a
successive approximation algorithm by the SAR starting
from the most signifi cant bit (MSB) to the least signifi cant
bit (LSB). The sampled input is successively compared
with binary weighted charges supplied by the capacitive
DAC using a differential comparator. At the end of a
conversion, the DAC output balances the analog input.
The SAR contents (a 12-bit data word) that represent the
sampled analog input are loaded into 12 output latches
that allow the data to be shifted out.
Programming the LTC2306 and LTC2302
The software compatible LTC2302/LTC2306/LTC2308 fam-
ily features a 6-bit D
IN
word to program various modes of
operation. Don’t care bits (X) are ignored. The SDI data
bits are loaded on the rising edge of SCK, with the S/D bit
loaded on the fi rst rising edge (see Figure 6 in the Timing