Datasheet

11
2188f
LTC2188
TiMing DiagraMs
Double Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
t
D
•
•
•
t
D
t
C
t
C
t
L
BIT 0
A-6
BIT 1
A-6
BIT 0
A-5
BIT 1
A-5
BIT 0
A-4
BIT 1
A-4
BIT 0
A-3
BIT 1
A-3
BIT 0
A-2
BIT 14
A-6
BIT 15
A-6
BIT 14
A-5
BIT 15
A-5
BIT 14
A-4
BIT 15
A-4
BIT 14
A-3
BIT 15
A-3
BIT 14
A-2
ENC
–
ENC
+
D1_0_1
+
D1_14_15
+
•
•
•
BIT 0
B-6
BIT 1
B-6
BIT 0
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
BIT 14
B-6
BIT 15
B-6
BIT 14
B-5
BIT 15
B-5
BIT 14
B-4
BIT 15
B-4
BIT 14
B-3
BIT 15
B-3
BIT 14
B-2
OF
B-6
OF
A-6
OF
B-5
OF
A-5
OF
B-4
OF
A-4
OF
B-3
OF
A-3
OF
B-2
D2_0_1
+
D2_14_15
+
CLKOUT
+
CLKOUT
–
OF2_1
+
D1_0_1
–
D1_14_15
–
D2_0_1
–
D2_14_15
–
OF2_1
–
2188 TD03
t
H
t
AP
A + 1
A + 2
A + 4
A + 3
A
CH 1
ANALOG
INPUT
t
AP
B + 1
B + 2
B + 4
B + 3
B
CH 2
ANALOG
INPUT