Datasheet

LTC2188
24
2188f
applicaTions inForMaTion
Phase Shifting the Output Clock
In Full Rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT
+
,
so the rising edge of CLKOUT
+
can be used to latch the
output data. In Double Data Rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT
+
. To allow adequate
set-up and hold time when latching the data, the CLKOUT
+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2188 can also phase shift the CLKOUT
+
/CLKOUT
–
signals by serially programming mode control register A2.
The output clock can be shifted by 0°, 45°, 90°, or 135°. To
use the phase shifting feature the clock duty cycle stabilizer
must be turned on. Another control register bit can invert
the polarity of CLKOUT
+
and CLKOUT
–
, independently of
the phase shift. The combination of these two features
enables phase shifts of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
A
IN
+
– A
IN
–
(2V Range) OF
D15-D0
(OFFSET BINARY)
D15-D0
(2’s COMPLEMENT)
>1.000000V
+0.999970V
+0.999939V
1
0
0
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1110
0111 1111 1111 1111
0111 1111 1111 1111
0111 1111 1111 1110
+0.000030V
+0.000000V
–0.000030V
–0.000061V
0
0
0
0
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
–0.999939V
–1.000000V
<–1.000000V
0
0
1
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0000
1000 0000 0000 0000
CLKOUT
+
D0-D15, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
0
0
0
1
1
1
1
CLKPHASE1
MODE CONTROL BITS
0
0
1
1
0
0
1
1
CLKPHASE0
0
1
0
1
0
1
0
1
2188 F14
ENC
+
Figure 14. Phase Shifting CLKOUT