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LT1122

1122fb

For more information www.linear.com/LT1122

TYPICAL APPLICATION

FEATURES DESCRIPTION

Fast Settling, JFET Input

Operational Amplifier

The LT

1122 JFET input operational amplifier combines

high speed and precision performance.

A unique poly-gate JFET process minimizes gate series

resistance and gate-to-drain capacitance, facilitating wide

bandwidth performance, without degrading JFET transis

tor matching.

slews at 80V/µs and settles in 340ns. The LT1122 is

internally compensated to be unity-gain stable, yet it has

a bandwidth of 14MHz at a supply current of only 7mA. Its

speed makes the LT1122 an ideal choice for fast settling

12-bit data conversion and acquisition systems.

The LT1122 offset voltage of 120µV, and voltage gain of

500,000 also support the 12-bit accurate applications.

The input bias current of 10pA and offset current of 4pA

combined with its speed allow the LT1122 to be used in

such applications as high speed sample and hold ampli

fiers, peak detectors, and integrators.

12-Bit Voltage Output D/A Converter Large-Scale Response

APPLICATIONS

100% Tested Settling Time 340ns Typ

to 1mV at Sum Node, 10V Step 540ns Max

Tested with Fixed Feedback Capacitor

Slew Rate 60V/µs Min

Gain-Bandwidth Product 14MHz

Power Bandwidth (20V

P-P

) 1.2 MHz

Unity-Gain Stable; Phase Margin 60°

Input Offset Voltage 600µV Max

Input Bias Current 25°C 75pA Max

70°C 600pA Max

■

Input Offset Current 25°C 40pA Max

70°C 150pA Max

■

Low Distortion

Fast 12-Bit D/A Output Amplifiers

High Speed Buffers

Fast Sample-and-Hold Amplifiers

High Speed Integrators

Voltage to Frequency Converters

Active Filters

Log Amplifiers

Peak Detectors

L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks and C-Load

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners.

0mA TO 2mA

OR 4mA

0V TO 10V

OUT

12-BIT CURRENT OUTPUT D/A CONVERTER

= 5pF TO 17pF

(DEPENDING ON D/A CONVERTER USED)

–

LT1122

LT1122•TA01

200ns/DIV

= –1

1122 TA07

5V/DIV

Summary of content (14 pages)

PAGE 1
LT1122 Fast Settling, JFET Input Operational Amplifier FEATURES n n n n n n n ■ ■ DESCRIPTION 100% Tested Settling Time 340ns Typ to 1mV at Sum Node, 10V Step 540ns Max Tested with Fixed Feedback Capacitor Slew Rate 60V/µs Min Gain-Bandwidth Product 14MHz Power Bandwidth (20VP-P) 1.
PAGE 2
LT1122 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage....................................................... ± 20V Differential Input Voltage........................................ ± 40V Input Voltage........................................................... ± 20V Output Short Circuit Duration........................... Indefinite Lead Temperature (Soldering, 10 sec.)................... 300°C Operating Temperature Range LT1122AM/BM/CM/DM (OBSOLETE)... –55°C to 125°C LT1122AC/BC/CC/DC/CS/DS...........
PAGE 3
LT1122 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = 0V unless otherwise noted.
PAGE 4
LT1122 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at 0°C ≤ TA ≤ 70°C. VS = ±15V, VCM = 0V.
PAGE 5
LT1122 ELECTRICAL CHARACTERISTICS Note 4: Input voltage range functionality is assured by testing offset voltage at the input voltage range limits to a maximum of 4mV (A, B grades), to 5.7mV (C, D grades). Note 5: Minimum supply voltage is tested by measuring offset voltage to 7mV maximum at ±5V supplies. Note 6: The LT1122 is not tested and not quality-assurance-sampled at –40°C and at 85°C.
PAGE 6
LT1122 TYPICAL PERFORMANCE CHARACTERISTICS Settling Time (Input from 0V to 10V) 1mV/DIV AT SUM NODE 1mV/DIV AT SUM NODE Settling Time (Input from 10V to 0V) 1mV/DIV AT SUM NODE Settling Time (Input from –10V to 0V) 100ns/DIV 1122 G01 100ns/DIV Settling Time (Input from 0V to –10V) 100ns/DIV 1122 G02 1122 G03 Undistorted Output Swing vs Frequency Large-Signal Response PEAK-TO-PEAK OUTPUT SWING (V) 5V/DIV 1mV/DIV AT SUM NODE 30 100ns/DIV AV = 1 1122 G04 200ns/DIV 1122 G05 VS = ±15V TA =
PAGE 7
LT1122 TYPICAL PERFORMANCE CHARACTERISTICS Distribution of Input Offset Voltage NUMBER OF UNITS 600 400 200 0 –900 –100 100 –500 100k 10k 3k BIAS CURRENT 1k 300 100 30 OFFSET CURRENT 10 3 1 900 500 120 VS = ±15V 30k VCM = 0V 25 0 50 75 VOLTAGE NOISE DENSITY (nV/√Hz) CHANGE IN OFFSET VOLTAGE (µV) SO PACKAGE N PACKAGE 150 J PACKAGE 100 50 IN STILL AIR (SO PACKAGE SOLDERED ONTO BOARD) 1 2 1 3 10 100 300 1k 3k 10k AV = –10 AV = –1 100 1k 10k 20k FREQUENCY (Hz) 15 4 6
PAGE 8
LT1122 APPLICATIONS INFORMATION Settling time test circuits shown on some competitive devices’ data sheets require: 1. A “flat top” pulse generator. Unfortunately, flat top pulse generators are not commercially available. 2. A variable feedback capacitor around the device under test. This capacitor varies over a four-to-one range. Presumably, as each op amp is measured for settling time, the capacitor is fine tuned to optimize settling time for that particular device.
PAGE 9
LT1122 TYPICAL APPLICATIONS Quartz Stabilized Oscillator With 9ppm Distortion OUTPUT –15V 4.7k LT1004 2.5V 15V + LT1122 430pF 50k 4.7k LT1010 – DISTORTION TRIM 5k + 4.7k 47k 4kHz J CUT OUTPUT AMPLITUDE 10µF TRIM MOUNT IN CLOSE PROXIMITY – LT1006 + 560k 470W 15V 2k – 1M 15V LT1122 + GROUND CRYSTAL CASE 560k = VACTEC VTL5C10 OR CLAIREX CLM410 –15V 1/4 LTC201 Q1 2N3904 100k = 1N4148 1122 TA05 1122fb For more information www.linear.
PAGE 10
LT1122 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. N Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510 Rev I) .400* (10.160) MAX 8 7 6 5 1 2 3 4 .255 ±.015* (6.477 ±0.381) .300 – .325 (7.620 – 8.255) .008 – .015 (0.203 – 0.381) ( +.035 .325 –.015 8.255 +0.889 –0.381 ) .045 – .065 (1.143 – 1.651) .065 (1.651) TYP .100 (2.54) BSC .130 ±.005 (3.302 ±0.127) .120 (3.048) .020 MIN (0.508) MIN .
PAGE 11
LT1122 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. J8 Package 3-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) CORNER LEADS OPTION (4 PLCS) .023 – .045 (0.584 – 1.143) HALF LEAD OPTION .045 – .068 (1.143 – 1.650) FULL LEAD OPTION .005 (0.127) MIN .405 (10.287) MAX 8 7 6 5 .025 (0.635) RAD TYP .220 – .310 (5.588 – 7.874) 1 .300 BSC (7.62 BSC) 2 3 4 .200 (5.080) MAX .015 – .060 (0.381 – 1.
PAGE 12
LT1122 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610 Rev G) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 .245 MIN .160 ±.005 .010 – .020 × 45° (0.254 – 0.508) NOTE: 1. DIMENSIONS IN 5 .150 – .157 (3.810 – 3.988) NOTE 3 1 RECOMMENDED SOLDER PAD LAYOUT .053 – .069 (1.346 – 1.752) 0°– 8° TYP .016 – .050 (0.406 – 1.
PAGE 13
LT1122 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION B 02/14 Updated data sheet to current standards. New Order Information Table, Package Descriptions PAGE NUMBER 2, 10-12 1122fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 14
LT1122 TYPICAL APPLICATION Wide-Band, Filtered, Full Wave Rectifier 200k 1% 1µF 200k 1% 20k 1% VIN 20k 1% 100k 1% 1k 50k – EOUT DC LT1122 – LT1122 + + OUTPUT DC = RMS VALUE OF INPUT BANDWIDTH WITH 10VP-P INPUT = 2MHz 1122 TA06 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1022 High Speed Precision JFET Op Amp 23V/µs Min Slew Rate, 250µV VOS LT1055/LT1056 Precision High Speed JFET Op Amps 16V/µs Slew Rate, 150µV VOS LT1464 1MHz C-Load™ Stable JFET Op Amp Capacitive Loads Up to 10n