Datasheet

LT1460
16
1460fc
LT1460-5
R
L
V
OUT
V
GEN
1460 F06
C
IN
0.1µF
5V
4V
C
L
V
IN
= 5V
2µs/DIV
5V
4V
R
L
= 10k
R
L
= 1k
1460 F07
V
GEN
V
OUT
V
OUT
10µs/DIV
5V
4V
R
L
= 10k
R
L
= 1k
1460 F08
V
GEN
V
OUT
V
OUT
C
L
= 1µF. R
S
should not be made arbitrarily large because
it will limit the load regulation.
Figure 6 to Figure 8 illustrate response in the LT1460-5.
The 1V step from 5V to 4V produces a current step of
1mA or 100µA for R
L
= 1k or R
L
= 10k. Figure 7 shows the
response of the reference with no load capacitance.
The reference settles to 5mV (0.1%) in less than 2µs for
a 100µA pulse and to 0.1% in 3µs with a 1mA step. When
load capacitance is greater than 0.01µF, the reference begins
to ring due to the pole formed with the output impedance.
Figure 8 shows the response of the reference to a 1mA
Figure 6. Response Time Test Circuit
Figure 8. C
L
= 0.01µF
Figure 7. C
L
= 0
and 100µA load current step with a 0.01µF load capacitor.
Figure 9 to Figure 11 illustrate response of the LT1460-10.
The 1V step from 10V to 9V produces a current step of
1mA or 100µA for R
L
= 1k or R
L
= 10k. Figure 10 shows
the response of the reference with no load capacitance.
The reference settles to 10mV (0.1%) in 0.4µs for a 100µA
pulse and to 0.1% in 0.8µs with a 1mA step. When load
capacitance is greater than 0.01µF, the reference begins
to ring due to the pole formed with the output impedance.
Figure 11 shows the response of the reference to a 1mA and
100µA load current step with a 0.01µF load capacitor.
Figure 11. C
L
= 0.01µF
Figure 10. C
L
= 0
Figure 9. Response Time Test Circuit
LT1460-10
R
L
V
OUT
V
GEN
1460 F09
C
IN
0.1µF
10V
9V
C
L
V
IN
= 12.5V
2µs/DIV
10V
9V
R
L
= 10k
R
L
= 1k
1460 F10
V
GEN
V
OUT
V
OUT
10µs/DIV
10V
9V
R
L
= 10k
R
L
= 1k
1460 F11
V
GEN
V
OUT
V
OUT
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