Datasheet

10
LT1641-1/LT1641-2
164112fc
SHORT
PIN
V
CC
TIMER
SENSE GATE
876
54
21
3
D1
CMPZ
5248B
GND
PWRGD
PWRGD
FB
R5
10Ω
5%
ON
R1
49.9k
1%
V
IN
24V
GND
1641-1 F10
R2
3.4k
1%
C2
0.68µF
D2
30V
1N5256B
R6,
1k, 5%
R
S
0.025Ω
C1
10nF
R3
59k
1%
R4
3.57k
1%
R7
24k
5%
+
C
L
V
OUT
LT1641-1
Q1
IRF530
Figure 10. Overvoltage Detection
Figure 11. Overvoltage Waveforms
APPLICATIO S I FOR ATIO
WUU
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Figure 9. Short-Circuit Waveforms
GATE Pin Voltage
A curve of gate drive vs V
CC
is shown in Figure 13. The
GATE pin is clamped to a maximum voltage of 18V above
the input voltage. At minimum input supply voltage of 9V,
the minimum gate drive voltage is 4.5V. When the input
supply voltage is higher than 20V, the gate drive voltage is
at least 10V and a regular N-FET can be used. In applica-
tions over a 9V to 24V range, a logic level N-FET must be
used with a proper protection Zener diode between its gate
and source (as D1 shown is Figure 5).