Datasheet

ManualsBrandsLinear Technology ManualsAmplifiers & ComparatorsComparator MSOP 12V/±6V

LT1715

1715fa

TYPICAL APPLICATION

DESCRIPTION

4ns, 150MHz

Dual Comparator with

Independent Input/Output Supplies

The LT

1715 is an UltraFast™ dual comparator optimized for

low voltage operation. Separate supplies allow independent

analog input ranges and output logic levels with no loss of

performance. The input voltage range extends from 100mV

below V

to 1.2V below V

. Internal hysteresis makes the

LT1715 easy to use even with slow moving input signals.

The rail-to-rail outputs directly interface toTTL and CMOS.

The symmetric output drive results in similar rise and fall

times that can be harnessed for analog applications or for

easy translation to other single supply logic levels.

The LT1715 is available in the 10-pin MSOP package. The

pinout of the LT1715 minimizes parasitic effects by placing

the most sensitive inputs away from the outputs, shielded

by the power rails.

For a dual/quad single supply comparator with simi-

lar propagation delay, see the LT1720/LT1721. For a

single comparator with similar propagation delay, see

the LT1719.

100MHz Dual Differential Line Receiver

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

UltraFast is a trademark of Linear Technology Corporation.

FEATURES

APPLICATIONS

UltraFast: 4ns at 20mV Overdriven

150MHz Toggle Frequency

Separate Input and Output Power Supplies

Low Power: 4.6mA per Comparator at 3V

Pinout Optimized for High Speed Use

Output Optimized for 3V and 5V Supplies

TTL/CMOS Compatible Rail-to-Rail Output

Input Voltage Range Extends 100mV

Below Negative Rail

Internal Hysteresis with Speciﬁ ed Limits

Speciﬁ ed for –40°C to 125°C Temperature Range

Available in the 10-pin MSOP Package

High Speed Differential Line Receivers

Level Translators

Window Comparators

Crystal Oscillator Circuits

Threshold Detectors/Discriminators

High Speed Sampling Circuits

Delay Lines

Line Receiver Response to 100MHz Clock,

50MHz Data Both with 25mV

P-P

Inputs

–

1715 TA01

IN A

OUT A

OUT B

–5V

5V 3V

IN B

5ns/DIV

1715 TA02

1V/DIV

CLOCK OUT

DATA OUT

FET PROBES

Downloaded from Arrow.com.

Summary of content (20 pages)

PAGE 1
LT1715 4ns, 150MHz Dual Comparator with Independent Input/Output Supplies DESCRIPTION FEATURES n n n n n n n n n n n UltraFast: 4ns at 20mV Overdriven 150MHz Toggle Frequency Separate Input and Output Power Supplies Low Power: 4.
PAGE 2
LT1715 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) Supply Voltage +VS to GND .............................................................7V VCC to VEE ..........................................................13.2V +VS to VEE ..........................................................13.2V VEE to GND ......................................... –13.2V to 0.3V Input Current (+IN, –IN) .......................................±10mA Output Current (Continuous) ...............................
PAGE 3
LT1715 ELECTRICAL CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VCC = 5V, VEE = –5V, +VS = 5V, VCM = 1V, COUT = 10pF, VOVERDRIVE = 20mV, unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage (Note 6) (Note 6) MIN LT1715C, LT1715I LT1715H l l LT1715C, LT1715I LT1715H l l 2 2 TYP MAX UNITS 0.4 2.5 3.5 4 mV mV mV 3.
PAGE 4
LT1715 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT1715C is guaranteed functional over the operating range of –40°C to 85°C. Note 3: The LT1715C is guaranteed to meet speciﬁed performance from 0°C to 70°C.
PAGE 5
LT1715 TYPICAL PERFORMANCE CHARACTERISTICS Quiescent Supply Current vs Temperature –1 –2 –3 –4 –5 –6 –7 –5 –4 –3 –2 –1 0 1 2 3 4 DIFFERENTIAL INPUT VOLTAGE (V) 5 VCC = +VS = 5V VEE = –5V 6 IS 4 2 ICC 0 –2 IEE –4 –6 –50 –25 75 50 25 TEMPERATURE (°C) 0 100 Output Low Voltage vs Load Current –0.1 OUTPUT VOLTAGE RELATIVE TO +VS (V) OUTPUT VOLTAGE (V) 0.4 125°C 0.3 –55°C 25°C 0.2 0.1 0 0 4 12 16 8 OUTPUT SINK CURRENT (mA) –0.2 –55°C –0.3 25°C –0.4 125°C –0.5 125°C +VS = 2.7V –0.
PAGE 6
LT1715 TYPICAL PERFORMANCE CHARACTERISTICS Maximum Toggle Rate vs Input Amplitude Maximum Toggle Rate vs Temperature 250 TOGGLE FREQUENCY (MHz) TA = 25°C 160 +VS = VCC = 5V VEE = GND 140 CLOAD = 10pF 120 100 80 60 40 20 250 TA = 25°C 230 VIN = ±50mV SINUSOID +VS = VCC = 5V 210 VEE = –5V 190 CLOAD = 10pF RLOAD = 500Ω 170 150 130 110 90 70 50 –50 0 10 INPUT SINUSOID AMPLITUDE (mV) 1 100 –25 50 25 0 75 TEMPERATURE (°C) 100 1715 G13 175 150 125 100 8 PROPAGATION DELAY (ns) TOGGLE FREQUENCY (MHz)
PAGE 7
VCM 1/2 LT1638 50Ω 100k 100k – 100k DUT 1/2 LT1715 + 100k 1/2 LT1638 200k 0.15μF 2.4k NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM ±15V. 200kΩ PULL-DOWN PROTECTS LTC203 LOGIC INPUTS WHEN DUT IS NOT POWERED 50Ω 50k 0.1μF + – + – Downloaded from Arrow.com. VCC BANDWIDTH-LIMITED TRIANGLE WAVE ~ 1kHz, VCM ±7.
PAGE 8
LT1715 TEST CIRCUITS Response Time Test Circuit +Vs – VCM 0V VCC – VCM 0.01μF –100mV 25Ω 25Ω 0.1μF 0V PULSE IN 50k 130Ω + DUT 1/2 LT1715 10× SCOPE PROBE (CIN ≈ 10pF) – 0.01μF 2N3866 1N5711 V1* 50Ω VEE – VCM –3V 50Ω 400Ω –5V 750Ω –VCM *V1 = –1000 • (OVERDRIVE + VTRIP+) NOTE: RISING EDGE TEST SHOWN. FOR FALLING EDGE, REVERSE LT1719 INPUTS 1715 TC02 1715fa 8 Downloaded from Arrow.com.
PAGE 9
LT1715 APPLICATIONS INFORMATION Power Supply Conﬁgurations The LT1715 has separate supply pins for the input and output stages that allow ﬂexible operation, accommodating separate voltage ranges for the analog input and the output logic. Of course, a single 3V/5V supply may be used by tying +VS and VCC together as well as GND and VEE. The minimum voltage requirement can be simply stated as both the output and the input stages need at least 2.7V and the VEE pin must be equal to or less than ground.
PAGE 10
LT1715 APPLICATIONS INFORMATION When both input signals are above the positive common mode limit, the input stage will get debiased and the output polarity will be random. However, the internal hysteresis will hold the output to a valid logic level. When at least one of the inputs returns to within the common mode limits, recovery from this state will take as long as 1μs.
PAGE 11
LT1715 APPLICATIONS INFORMATION The ground trace from Pin 6 runs under the device up to the bypass capacitor, shielding the inputs from the outputs. Note the use of a common via for the LT1715 and the bypass capacitors, which minimizes interference from high frequency energy running around the ground plane or power distribution traces. The supply bypass should include an adjacent 10nF ceramic capacitor and a 2.
PAGE 12
LT1715 APPLICATIONS INFORMATION Unused Comparators If a comparator is unused, its output should be left ﬂoatingto minimize load current. The unused inputs can be tied off to the rails and power consumption can be further minimized if the inputs are connected to the power rails to induce an output low. Connecting the inverting input to VCC and the noninverting input to VEE will likely be the easiest method.
PAGE 13
LT1715 APPLICATIONS INFORMATION power translator can be constructed with resistors as shown in Figure 8. VREF R2´ VTH R3 VAVERAGE = +VS 2 R1 + 1/2 LT1715 – 1715 F07 Figure 7. Model for Additional Hysteresis Calculations The second step is to recalculate R2 to set the same average threshold as before. The average threshold before was set at VTH = (VREF)(R1)/(R1 + R2). The new R2 is calculated based on the average output voltage (+VS /2)and the simpliﬁed circuit model in Figure 7.
PAGE 14
LT1715 APPLICATIONS INFORMATION tors. Not only can they foul up the operation of the ECL gate because of overshoots, they can damage the ECL inputs, particularly during power-up of separate supply conﬁgurations. Of course, if the VEE of the LT1715 is the same as the ECL negative supply, the GND pin can be tied to it as well and +VS grounded. Then the output stage has the same powerrails as the ECL and the circuits of Figure 8b can be used. The level translator designs assume one gate load.
PAGE 15
LT1715 APPLICATIONS INFORMATION ECL, and particularly PECL, is valuable technology for high speed system design, but it must be used with care. With less than a volt of swing, the noise margins need to be evaluated carefully. Note that there is some degradation of noise margin due to the ±5% resistor selections shown. With 10KH/E, there is no temperature compensation of the logic levels, whereas the LT1715 and the circuits shown give levels that are stable with temperature.
PAGE 16
LT1715 APPLICATIONS INFORMATION The bias conditions and signal swings in the output stage are designed to turn their respective output transistors off faster than on. This helps minimize the surge of current from +VS to ground that occurs at transitions, to minimize the frequency-dependent increase in power consumption. The frequency dependence of the supply current is shown in the Typical Performance Characteristics.
PAGE 17
LT1715 APPLICATIONS INFORMATION The gain and hysteresis stage of the LT1715 is simple, short and high speed to help prevent parasitic oscillations while adding minimum dispersion. This internal “self-latch” can be usefully exploited in many applications because it occurs early in the signal chain, in a low power, fully differential stage. It is therefore highly immune to disturbances from other parts of the circuit, such as the output, or on the supply lines.
PAGE 18
LT1715 GND VEE 150Ω +IN –IN VCC 150Ω 1715 SS +VS OUTPUT SIMPLIFIED SCHEMATIC 1715fa 18 Downloaded from Arrow.com.
PAGE 19
LT1715 PACKAGE DESCRIPTION MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.497 ± 0.076 (.0196 ± .003) REF 10 9 8 7 6 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.86 (.
PAGE 20
LT1715 TYPICAL APPLICATION Propagation delay of comparators is typically speciﬁed fora 100mV step with some fraction of that for overdrive. But in many signal processing applications, such as in communications, the goal is to convert a sine wave, such as a carrier, to a square wave for use as a timing clock. The desired behavior is for the output timing to be dependent on the input timing only. No phase shift should occur as a function of the input amplitude, which would result in AM to FM conversion.