Datasheet

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LT1719

1719fa

TYPICAL APPLICATION

FEATURES DESCRIPTION

APPLICATIONS

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. UltraFast is a trademark of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

OVERDRIVE (mV)

DELAY (ns)

1719 TA02

10 20 40

25°C

STEP

= 100mV

= 5V

LOAD

= 10pF

RISING EDGE

PDLH

)

FALLING EDGE

PDHL

)

UltraFast: 4.5ns at 20mV Overdrive

7ns at 5mV Overdrive

Low Power: 4.2mA at 3V

Separate Input and Output Power Supplies

(SO-8 Only)

Output Optimized for 3V and 5V Supplies

TTL/CMOS Compatible Rail-to-Rail Output

Low Power Shutdown Mode: 0.1μA

Low Proﬁ le (1mm) SOT-23 (ThinSOT™) Package

The LT

1719 is an UltraFast™ comparator optimized for low

voltage operation. The input voltage range extends from

100mV below V

to 1.2V below V

. Internal hysteresis

makes the LT1719 easy to use even with slow moving input

signals. The rail-to-rail outputs directly interface to TTL

and CMOS. Alternatively the symmetric output drive can be

harnessed for analog applications or for easy translation to

other single supply logic levels. A shutdown control allows

for reduced power consumption and extended battery life

in portable applications.

The LT1719 is available in the SO-8 and 6-lead SOT-23

package. The SO-8 package has separate supplies which

allow ﬂ exible operation, accomodating separate analog

input ranges and output logic levels.

For a dual/quad comparator with similar performance, see

the LT1720/LT1721.

High Speed Differential Line Receiver

Crystal Oscillator Circuits

Level Translators

Threshold Detectors/Discriminators

Zero-Crossing Detectors

High Speed Sampling Circuits

Delay Lines

2.7V to 6V Crystal Oscillator with TTL/CMOS Output

Propagation Delay vs Overdrive

–

LT1719

2.7V TO 6V

620Ω

220Ω

1MHz TO 10MHz

CRYSTAL (AT-CUT)

1719 TA01

0.1μF 1.8k

OUTPUT

GROUND

CASE

4.5ns Single/Dual Supply

3V/5V Comparator with

Rail-to-Rail Output

Summary of content (22 pages)

PAGE 1
LT1719 4.5ns Single/Dual Supply 3V/5V Comparator with Rail-to-Rail Output DESCRIPTION FEATURES n n n n n n n UltraFast: 4.5ns at 20mV Overdrive 7ns at 5mV Overdrive Low Power: 4.2mA at 3V Separate Input and Output Power Supplies (SO-8 Only) Output Optimized for 3V and 5V Supplies TTL/CMOS Compatible Rail-to-Rail Output Low Power Shutdown Mode: 0.
PAGE 2
LT1719 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage + VS to GND (LT1719S8) ........................................ 7V VCC to VEE (LT1719S8) ........................................ 12V +VS to VEE (LT1719S8) ....................................... 12V VEE to GND (LT1719S8) ....................... –12V to 0.3V V+ to V– (LT1719S6) ...............................................7V Input Current (+IN, –IN or SHDN) ...................... ±10mA Output Current (Continuous) ...........................
PAGE 3
LT1719 ELECTRICAL CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VCM = 1V, VSHDN = 0.5V, VOVERDRIVE = 20mV, COUT = 10pF and for the LT1719S8 VCC = +VS = 5V and VEE = –5V, for the LT1719S6 V+ = 5V, V– = 0V, unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS VCC – VEE Input Supply Voltage + VS Output Supply Voltage MIN MAX UNITS (LT1719S8 Only) l 2.7 10.5 V (LT1719S8 Only) l 2.
PAGE 4
LT1719 ELECTRICAL CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VCM = 1V, VSHDN = 0.5V, VOVERDRIVE = 20mV, COUT = 10pF and for the LT1719S8 VCC = +VS = 5V and VEE = –5V, for the LT1719S6 V+ = 5V, V– = 0V, unless otherwise speciﬁed. SYMBOL PARAMETER IS CONDITIONS Positive Output Stage Supply Current MIN + VS = VCC = 5V, VEE = –5V Supply Current ISHDN5 (LT1719S6) Shutdown Pin Current 8 mA 6 mA 4.
PAGE 5
LT1719 TYPICAL PERFORMANCE CHARACTERISTICS Input Offset and Trip Voltages vs Supply Voltage Input Offset and Trip Voltages vs Temperature 4.2 3 2 1 VOS 0 –1 VTRIP– 25°C VCM = 1V VEE OR V– = GND –2 –3 2.5 VTRIP 2 + COMMON MODE INPUT VOLTAGE (V) VTRIP+ VOS AND TRIP POINT VOLTAGE (mV) 1 VOS 0 –1 –2 VTRIP– + +VS = VCC or V = 5V VCM = 1V VEE OR V– = GND –3 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 5.5 6.0 3.0 3.5 4.0 4.5 5.
PAGE 6
LT1719 TYPICAL PERFORMANCE CHARACTERISTICS 0.5 Output High Voltage vs Load Current OUTPUT VOLTAGE RELATIVE TO +VS (V) +VS OR V+ = 5V VIN = –10mV OUTPUT VOLTAGE (V) 125°C 0.4 125°C VCC = 2.7V 25°C 0.3 –55°C 0.2 0.1 4 12 16 8 OUTPUT SINK CURRENT (mA) –55°C 25°C –0.4 –0.6 –0.
PAGE 7
LT1719 PIN FUNCTIONS LT1719S8 LT1719S6 VCC (Pin 1): Positive Supply Voltage for Input Stage. –IN (Pin 1): Inverting Input of Comparator. + IN (Pin 2): Noninverting Input of Comparator. V – (Pin 2): Negative Supply, Usually Grounded. –IN (Pin 3): Inverting Input of Comparator. + IN (Pin3): Noninverting Input of Comparator. VEE (Pin 4): Negative Supply Voltage for Input Stage and Chip Substrate. V+ (Pin 4): Positive Supply Voltage. GND (Pin 5): Ground. SHDN (Pin 6): Shutdown.
PAGE 8
LT1719 TEST CIRCUITS Response Time Test Circuit +Vs – VCM (V+ – VCM) 0V VCC – VCM –100mV 1 25Ω 25Ω 0.1μF PULSE IN 0V 2 50k 3 130Ω V1* 2N3866 0.01μF 8 + DUT LT1719S8 – 5 4 50Ω 7 10 × SCOPE PROBE (CIN ≈ 10pF) 6(6) 0.01μF VEE – VCM 1N5711 –3V 50Ω –VCM 750Ω 400Ω *V1 = –1000 • (OVERDRIVE + VTRIP+) NOTE: RISING EDGE TEST SHOWN. FOR FALLING EDGE, REVERSE LT1719 INPUTS –5V 1719 TC02 ±VTRIP Test Circuit LTC203 BANDWIDTH-LIMITED TRIANGLE WAVE ~ 1kHz, VCM ±7.
PAGE 9
LT1719 APPLICATIONS INFORMATION Power Supply Conﬁgurations (SO-8 Package) The LT1719S8 has separate supply pins for the input and output stages that allow ﬂexible operation, accommodating separate voltage ranges for the analog input and the output logic. Of course, a single 3V/5V supply may be used by tying + VS and VCC together as well as GND and VEE. The minimum voltage requirement can be simply stated as both the output and the input stages need at least 2.
PAGE 10
LT1719 APPLICATIONS INFORMATION The propagation delay does not increase signiﬁcantly when driven with large differential voltages, but with low levels of overdrive, an apparent increase may be seen with large source resistances due to an RC delay caused by the 2pF typical input capacitance. Input Protection The input stage is protected against damage from large differential signals, up to and beyond a differential voltage equal to the supply voltage, limited only by the absolute maximum currents noted.
PAGE 11
LT1719 APPLICATIONS INFORMATION Shutdown Control The LT1719 features a shutdown control pin for reduced quiescent current when the comparator is not needed. During shutdown, the inputs and the outputs become high impedances. The LT1719 is enabled when the shutdown input is pulled low with a threshold roughly two diode drops below + VS or V+. Therefore, if driven by a standard TTL gate, a pull-up resistor should be used. Because shutdown is active high, this resistor adds little power drain during shutdown.
PAGE 12
LT1719 APPLICATIONS INFORMATION The exact amount of hysteresis will vary from part to part as indicated in the speciﬁcations table. The hysteresis level will also vary slightly with changes in supply voltage and common mode voltage. A key advantage of the LT1719 is the signiﬁcant reduction in these effects, which is important whenever an LT1719 is used to detect a threshold crossing in one direction only.
PAGE 13
LT1719 APPLICATIONS INFORMATION With this in mind, calculation of the resistor values needed is a two-step process. First, calculate the value of R3 based on the additional hysteresis desired, the output voltage swing and the impedance of the primary bias string: For additional hysteresis of 10mV or less, it is not uncommon for R2ʹ to be the same as R2 within 1% resistor tolerances. This method will work for additional hysteresis of up to a few hundred millivolts.
PAGE 14
LT1719 APPLICATIONS INFORMATION Figure 6a shows the standard TTL to Positive ECL (PECL) resistive level translator. This translator cannot be used for the LT1719, or with CMOS logic, because it depends on the 820Ω resistor to limit the output swing (VOH) of the all-NPN TTL gate with its so-called totem-pole output. The LT1719 is fabricated in a complementary bipolar process and the output stage has a PNP driver that pulls the output nearly all the way to the supply rail, even when sourcing 10mA.
PAGE 15
LT1719 APPLICATIONS INFORMATION Figure 6b shows a three resistor level translator for interfacing the LT1719 to ECL running off the same supply rail. No pull-down on the output of the LT1719 is needed, but pull-down R3 limits the VIH seen by the PECL gate. This is needed because ECL inputs have both a minimum and maximum VIH speciﬁcation for proper operation. Resistor values are given for both ECL interface types; in both cases it is assumed that the LT1719 operates from the same supply rail.
PAGE 16
LT1719 APPLICATIONS INFORMATION Circuit Description The block diagram of the LT1719 is shown in Figure 7. The circuit topology consists of a differential input stage, a gain stage with hysteresis and a complementary common-emitter output stage. All of the internal signal paths utilize low voltage swings for high speed at low power.
PAGE 17
LT1719 APPLICATIONS INFORMATION three categories: input speed limits, output speed limits, and internal speed limits. high toggle frequency applications, consider the LT1394, whose linear output stage can toggle at 100MHz typical. There are no signiﬁcant input speed limits except the shunt capacitance of the input nodes. If the 2pF typical input nodes are driven, the LT1719 will respond. The internal speed limits manifest themselves as dispersion.
PAGE 18
LT1719 APPLICATIONS INFORMATION ±VTRIP Test Circuit The input trip points test circuit uses a 1kHz triangle wave to repeatedly trip the comparator being tested. The LT1719 output is used to trigger switched capacitor sampling of the triangle wave, with a sampler for each direction. Because the triangle wave is attenuated 1000:1 and fed to the LT1719’s differential input, the sampled voltages are therefore 1000 times the input trip voltages.
PAGE 19
VEE (V–) +IN –IN VCC (V+) SHDN 150Ω 150Ω 15k TO BIAS SOURCES 1719 SS GND (V–) OUTPUT +VS (V+) LT1719 SIMPLIFIED SCHEMATIC 1719fa 19
PAGE 20
LT1719 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 .245 MIN 7 6 5 .160 ±.005 .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) .030 ±.005 TYP 1 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) 0°– 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN .053 – .069 (1.346 – 1.752) .014 – .019 (0.355 – 0.
PAGE 21
LT1719 PACKAGE DESCRIPTION S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) 1.90 BSC S6 TSOT-23 0302 REV B NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3.
PAGE 22
LT1719 TYPICAL APPLICATION High Performance Sine Wave to Square Wave Converter Propagation delay of comparators is typically speciﬁed for a 100mV step with some fraction of that for overdrive. But in many signal processing applications, such as in communications, the goal is to convert a sine wave, such as a carrier, to a square wave for use as a timing clock. The desired behavior is for the output timing to be dependent on the input timing only.