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LT1737

1737fa

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

APPLICATIO S

FEATURES

DESCRIPTIO

High Power

Isolated Flyback Controller

The LT

1737 is a monolithic switching regulator control-

ler specifically designed for the isolated flyback topology.

It drives the gate of an external MOSFET and is generally

powered from a DC supply voltage. Output voltage feed-

back information may be supplied by a variety of methods

including a third transformer winding, the primary wind-

ing or even direct DC feedback (see Applications Informa-

tion). Its gate drive capability, coupled with a suitable

external MOSFET and other power path components, can

deliver load power up to tens of Watts.

The LT1737 has a number of features not found on other

isolated flyback controller ICs. By utilizing current mode

switching techniques, it provides excellent AC and DC line

regulation. Its unique control circuitry can maintain regu-

lation well into discontinuous mode in most applications.

Optional load compensation circuitry allows for improved

load regulation. An optional undervoltage lockout pin

halts operation when the application input voltage is too

low. An optional external capacitor implements a soft-

start function.

■

Drives External Power MOSFET

■

Supply Voltage Range: 4.5V to 20V

■

Flyback Voltage Limited Only by

External Components

■

Senses Output Voltage Directly from Primary Side

Winding—No Optoisolator Required

■

Switching Frequency from 50kHz to 250kHz

with External Capacitor

■

Moderate Accuracy Regulation Without User Trims

■

Regulation Maintained Well into Discontinuous Mode

■

External I

SENSE

Resistor

■

Optional Load Compensation

■

Optional Undervoltage Lockout

■

Shutdown Feature Reduces I

to 50µA Typ

■

Available in 16-Pin GN and SO Packages

■

Isolated Flyback Switching Regulators

■

Medical Instruments

■

Instrumentation Power Supplies

12V-18V to Isolated 15V Converter

PGND

SENSE

GATE

0.27Ω

IRFL014

COILTRONICS

CTX150-4

UVLO

SGND

1737 TA01

CMPC

OCMP

MINENAB

LT1737

ENDLYOSCAP t

3.01k

0.1µF

•

MBRS1100

33µF

7.5k

OUT

= 15V

OUT

= 300mA

BAS16

2N3906

35.7k

22µF

150µH 150µH

240k

33k

1nF

47pF

75k 150k 100k 4.7k 0.1µF

NOTE: SEE APPLICATIONS

INFORMATION FOR ADDITIONAL

COMPONENT SPECIFICATIONS

TYPICAL APPLICATIO

Summary of content (28 pages)

PAGE 1
LT1737 High Power Isolated Flyback Controller U FEATURES DESCRIPTIO ■ The LT®1737 is a monolithic switching regulator controller specifically designed for the isolated flyback topology. It drives the gate of an external MOSFET and is generally powered from a DC supply voltage. Output voltage feedback information may be supplied by a variety of methods including a third transformer winding, the primary winding or even direct DC feedback (see Applications Information).
PAGE 2
LT1737 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) VCC Supply Voltage ................................................. 22V UVLO Pin Voltage .................................................... VCC ISENSE Pin Voltage .................................................... 2V FB Pin Current ..................................................... ±2mA Operating Junction Temperature Range LT1737C ............................................... 0°C to 100°C LT1737I ...............
PAGE 3
LT1737 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.90 0.80 1.12 ● 1.25 1.35 V V 220 200 250 ● 270 280 220 mV mV mV 0.
PAGE 4
LT1737 U W TYPICAL PERFOR A CE CHARACTERISTICS 125 4.2 100 4.1 4.0 1.0 SHUTDOWN VOLTAGE VUVLO (V) 4.3 75 50 25 3.9 3.8 –50 –25 50 25 0 75 TEMPERATURE (°C) 0 –50 –25 125 100 50 25 0 75 TEMPERATURE (°C) 9 –1 –2 VUVLO = 1.3V –3 –4 –5 –6 –50 –25 125 100 50 25 75 0 TEMPERATURE (°C) VGATE vs ISINK 100 1.0 –0.5 VCC-VGATE (V) –1.0 TA = 25°C TA = 125°C TA = 25°C –1.5 0.4 –2.
PAGE 5
LT1737 U W TYPICAL PERFOR A CE CHARACTERISTICS Minimum Enable Time vs Temperature Minimum Switch On Time vs Temperature 275 MINIMUM ENABLE TIME (ns) 250 225 200 175 150 250 250 225 200 175 150 50 25 75 0 TEMPERATURE (°C) 100 125 125 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 1737 G10 60 40 TA = –55°C 0 –20 TA = 125°C –40 –60 –80 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.
PAGE 6
LT1737 U U U PI FU CTIO S PGND (Pin 1): The power ground pin carries the GATE node discharge current. This is typically a current spike of several hundred mA with a duration of tens of nanoseconds. It should be connected directly to a good quality ground plane. ISENSE (Pin 2): Pin to measure switch current with external sense resistor. The sense resistor should be of a noninductive construction as high speed performance is essential.
PAGE 7
LT1737 W BLOCK DIAGRA VCC 3VOUT UVLO BIAS 3V REG (INTERNAL) tON MINENAB ENDLY OSCAP GATE MOSFET DRIVER LOGIC OSC PGND ISENSE COMP IAMP SGND FB FDBK SOFT-START LOAD COMPENSATION 1737 BD VC SFST ROCMP RCMPC 1737fa 7
PAGE 8
LT1737 WU W TI I G DIAGRA VSW VOLTAGE COLLAPSE DETECT VFLBK 0.
PAGE 9
LT1737 U OPERATIO The LT1737 is a current mode switcher controller IC designed specifically for the isolated flyback topology. The Block Diagram shows an overall view of the system. Many of the blocks are similar to those found in traditional designs, including: Internal Bias Regulator, Oscillator, Logic, Current Amplifier and Comparator, Driver and Output Switch. The novel sections include a special Flyback Error Amplifier and a Load Compensation mechanism.
PAGE 10
LT1737 U OPERATIO Enable Delay Minimum Enable Time When the output switch shuts off, the flyback pulse appears. However, it takes a finite time until the transformer primary side voltage waveform approximately represents the output voltage. This is partly due to finite rise time on the MOSFET drain node, but more importantly, due to transformer leakage inductance. The latter causes a voltage spike on the primary side not directly related to output voltage.
PAGE 11
LT1737 U OPERATIO transformer secondary and output capacitor. This has been represented previously by the expression “ISEC • ESR.” However, it is generally more useful to convert this expression to an effective output impedance. Because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the lumped secondary impedance times the inverse of the OFF duty cycle.
PAGE 12
LT1737 U W U U APPLICATIO S I FOR ATIO TRANSFORMER DESIGN CONSIDERATIONS Transformer specification and design is perhaps the most critical part of applying the LT1737 successfully. In addition to the usual list of caveats dealing with high frequency isolated power supply transformer design, the following information should prove useful.
PAGE 13
LT1737 U W U U APPLICATIO S I FOR ATIO which reduces the size of the primary-referred flyback pulse used for feedback. This will increase the output voltage target by a similar percentage. Note that unlike leakage spike behavior, this phenomena is load independent. To the extent that the secondary leakage inductance is a constant percentage of mutual inductance (over manufacturing variations), this can be accommodated by adjusting the feedback resistor divider ratio.
PAGE 14
LT1737 U W U U APPLICATIO S I FOR ATIO 1000 SELECTING OSCILLATOR CAPACITOR VALUE 500 TIME (ns) The switching frequency of the LT1737 is set by an external capacitor connected between the OSCAP pin and ground. Recommended values are between 200pF and 33pF, yielding switching frequencies between 50kHz and 250kHz. Figure 2 shows the nominal relationship between external capacitance and switching frequency.
PAGE 15
LT1737 U W U U APPLICATIO S I FOR ATIO implications regarding output voltage regulation at minimum load (see Minimum Load Considerations). A second benefit of the enable delay time function occurs at light load. Under such conditions the amount of energy stored in the transformer is small. The flyback waveform becomes “lazy” and some time elapses before it indicates the actual secondary output voltage (see Figure 4C).
PAGE 16
LT1737 U W U U APPLICATIO S I FOR ATIO this frequency the sense resistor will behave like an inductor. Several techniques can be used to tame this potential parasitic inductance problem. First, any resistor used for current sensing purposes must be of an inherently noninductive construction. Mounting this resistor directly above an unbroken ground plane and minimizing its ground side connection will serve to absolutely minimize parasitic inductance.
PAGE 17
LT1737 U W U U APPLICATIO S I FOR ATIO VIN R1/2 VIN VIN R1 C2 R1 UVLO R2 R1/2 UVLO C1 100pF UVLO C1 100pF R2 R2 1737 F06 (6a) “Standard” UVLO Divider Topology (6b) Filter Capacitor Directly on UVLO Note (6c) Recommended Topology to Filter High Frequency Ripple Figure 6 FREQUENCY COMPENSATION Internal Voltage Reference Loop frequency compensation is performed by connecting a capacitor from the output of the error amplifier (VC pin) to ground.
PAGE 18
LT1737 U W U U APPLICATIO S I FOR ATIO Output Impedance Error An additional error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier, transformer secondary and output capacitor. Because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the “DC” lumped secondary impedance times the inverse of the off duty cycle.
PAGE 19
LT1737 U W U U APPLICATIO S I FOR ATIO MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS The LT1737 is a current mode controller. It uses the VC node voltage as an input to a current comparator that turns off the output switch on a cycle-by-cycle basis as this peak current is reached. The internal clamp on the VC node, nominally 2.5V, then acts as an output switch peak current limit. This 2.5V at the VC pin corresponds to a value of 250mV at the ISENSE pin, when the (ON) switch duty cycle is less than 40%.
PAGE 20
LT1737 U W U U APPLICATIO S I FOR ATIO the power paths (primary and secondary). B field (magnetic) radiation is minimized by keeping MOSFET leads, output diode and output bypass capacitor leads as short as possible. E field radiation is kept low by minimizing the length and area of all similar traces. A ground plane should always be used under the switcher circuitry to prevent interplane coupling.
PAGE 21
LT1737 U TYPICAL APPLICATIO S BASIC APPLICATION WITH 3-WINDING TRANSFORMER Figure 8 shows a compact, low power application of the LT1737. Transformer T1 is an off-the-shelf VERSA-PACTM, #VP1-0190, produced by Coiltronics. As manufactured, it consists of six ideally identical independent windings. In this application, two windings are stacked in series on the primary side and three are placed in parallel on the secondary side.
PAGE 22
LT1737 U TYPICAL APPLICATIO S Overall power supply efficiency and output regulation versus input voltage and load current may be seen in Figures 9 and 10. Available output current is a function of input voltage, varying from 650mA with 8V input to 1100mA with 25V input. In cases when the output switching noise is objectionable, the optional output L/C filter shown may be added. The oscilloscope photos in Figure 11 show the dramatic reduction in output voltage ripple with the optional filter.
PAGE 23
LT1737 U TYPICAL APPLICATIO S make this a preferable alternative. Furthermore, a variety of manufacturers offer off-the-shelf dual wound magnetics which often can be applied as 1:1 transformers.) APPLICATION WITH 2-WINDING TRANSFORMER The previous application example utilized a 3-winding transformer, the third winding providing only feedback information. Additional circuitry may be employed to provide feedback information, thus allowing the transformer to be reduced to a 2-winding topology.
PAGE 24
LT1737 U TYPICAL APPLICATIO S R3 and D2. (Diode D2 prevents reverse emitter/base breakdown in Q1 when MOSFET M1 is in the “ON” state.) The raw flyback voltage at the drain of MOSFET M1 minus the VBE of Q1 is converted to a current by R2 and then back to a voltage at R3. Or, stated mathematically: 5VIN APPLICATION The LT1737 is a bipolar technology IC specified to operate down to a minimum input supply voltage of 4.5V.
PAGE 25
LT1737 U TYPICAL APPLICATIO S therefore requires a physically larger transformer. The largest size VERSA-PAC is used, a VP5-0083. Three windings are paralleled for both the primary and secondary. Overall power supply efficiency and output regulation versus load current at the nominal VIN = 5V may be seen in Figures 16 and 17. 90 80 EFFICIENCY (%) 70 60 50 40 30 20 0.01 0.1 1 10 ILOAD (A) 1737 F16 Figure 16. Efficiency vs ILOAD OUTPUT VOLTAGE (V) 5.
PAGE 26
LT1737 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.009 (0.229) REF 0.053 – 0.068 (1.351 – 1.727) 2 3 4 5 6 7 8 0.004 – 0.0098 (0.102 – 0.249) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.
PAGE 27
LT1737 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 2 3 4 5 6 0.053 – 0.069 (1.346 – 1.752) 0.008 – 0.010 (0.203 – 0.254) 0.014 – 0.019 (0.355 – 0.483) TYP 8 0.004 – 0.010 (0.101 – 0.254) 0° – 8° TYP 0.016 – 0.
PAGE 28
LT1737 U TYPICAL APPLICATIO S VIN R3 26.1k 1% C7 47pF 50V NPO C8 0.1µF 25V Z5U R8 160k 5% R4 3.