7
LT1777
BLOCK DIAGRA
W
V
C
V
BG
LOGIC
FEEDBACK
AMP
SWDR
I
1
V
IN
V
D
V
SW
I
2
1777 BD
R1
V
B
V
BG
R
SENSE
I
SWON
OSC
SYNC
SHDN
V
CC
SGND
FB
BIAS
I
COMP
I
g
m
–dV/dt
LIMITER
±dI/dt
LIMITER
Q2
Q1
4
3
12
7
14
13
5
6
10
OUTPUT STAGE SI PLIFIED SCHE ATIC
WW
+
Q3Q2
R1
C1
Q4
Q6
SWITCH ON
SIGNAL
Q1
Q5
R2
V
SW
V
OUT
V
IN
L
SENSE
L
MAIN
R3
NOTE: R3 = R4
R4
1777 SS
V
D
I
1
I
