Datasheet

7
LT1785/LT1785A
LT1791/LT1791A
FU CTIO TABLES
UU
Figure 3. Driver/Receiver Timing Test Circuit Figure 4. Driver Timing Test Load
5V
DE
A
B
DI
R
DIFF
C
L1
C
L2
RO
15pF
A
B
RE
1785/91 F03
OUTPUT
UNDER TEST
C
L
S1
S2
V
CC
500Ω
1785/91 F04
LT1785 Transmitting
INPUTS OUTPUTS
RE DE DI A B RO
0100 10
0111 01
1 0 X Hi-Z Hi-Z Hi-Z
1100 1Hi-Z
1111 0Hi-Z
LT1785 Receiving
INPUTS OUTPUT
RE DE DI A-B RO
00X≤–200mV 0
00X≥200mV* 1
0 0 X Open 1
1 0 X X Hi-Z
* ≥ 0mV for LT1785A
LT1791
INPUTS OUTPUTS
RE DE DI A-B Y Z RO
00 X≤ –200mV Hi-Z Hi-Z 0
00 X≥200mV* Hi-Z Hi-Z 1
0 0 X Open Hi-Z Hi-Z 1
01 0≤ –200mV 0 1 0
01 0≥200mV* 0 1 1
0 1 0 Open 0 1 1
01 1≤ –200mV 1 0 0
01 1≥200mV* 1 0 1
0 1 1 Open 1 0 1
1 0 X X Hi-Z Hi-Z Hi-Z
1 1 0 X 0 1 Hi-Z
1 1 1 X 1 0 Hi-Z
* ≥ 0mV for LT1791A
TEST CIRCUITS
Figure 5. Driver Propagation Delays
DI
5V
1.5V
t
PLH
t
r
t
SKEW
1/2 V
O
V
O
f = 125kHz, t
r
≤ 10ns, t
f
≤ 10ns
90%
10%
0V
B
A
V
O
–V
O
0V
90%
1.5V
t
PHL
t
SKEW
1/2 V
O
10%
t
f
V
DIFF
= V(A) – V(B)
1785/91 F05
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