Datasheet

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LT1792

Low Noise, Precision,

JFET Input Op Amp

The LT

1792 achieves a new standard of excellence in

noise performance for a JFET op amp. The 4.2nV/√Hz

voltage noise combined with low current noise and

picoampere bias currents make the LT1792 an ideal choice

for amplifying low level signals from high impedance

capacitive transducers.

The LT1792 is unconditionally stable for gains of 1 or more,

even with load capacitances up to 1000pF. Other key

features are 600µV V

and a voltage gain of over 4 million.

Each individual amplifier is 100% tested for voltage noise,

slew rate and gain bandwidth.

The design of the LT1792 has been optimized to achieve

true precision performance with an industry standard

pinout in the SO-8 package. Specifications are also pro-

vided for ±5V supplies.

■

100% Tested Low Voltage Noise: 6nV/√Hz Max

■

A Grade 100% Temperature Tested

■

Voltage Gain: 1.2 Million Min

■

Offset Voltage Over Temp: 800µV Max

■

Gain-Bandwidth Product: 5.6MHz Typ

■

Guaranteed Specifications with ±5V Supplies

, LTC and LT are registered trademarks of Linear Technology Corporation.

Low Noise Hydrophone Amplifier with DC Servo

–

5V TO 15V

–5V TO –15V

0.47µF

100M

100k

LT1792

LT1097

3.9k

C1*

R1*

100M

200Ω

HYDRO-

PHONE

OUTPUT

DC OUTPUT ≤ 2.5mV FOR T

< 70°C

OUTPUT VOLTAGE NOISE = 128nV/√Hz AT 1kHz (GAIN = 20)

C1 ≈ C

≈ 100pF TO 5000pF; R4C2 > R8C

; *OPTIONAL

1792 TA01

INPUT VOLTAGE NOISE (nV/√Hz)

3.6

PERCENT OF UNITS (%)

4.0

4.4

4.6 5.6

1792 TA02

3.8 4.2

4.8

5.0

5.2

5.4

= ±15V

= 25°C

270 OP AMPS TESTED

1kHz Input Noise Voltage Distribution

■

Photocurrent Amplifiers

■

Hydrophone Amplifiers

■

High Sensitivity Piezoelectric Accelerometers

■

Low Voltage and Current Noise Instrumentation

Amplifier Front Ends

■

Two and Three Op Amp Instrumentation Amplifiers

■

Active Filters

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

Summary of content (12 pages)

PAGE 1
LT1792 Low Noise, Precision, JFET Input Op Amp U FEATURES ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT®1792 achieves a new standard of excellence in noise performance for a JFET op amp. The 4.2nV/√Hz voltage noise combined with low current noise and picoampere bias currents make the LT1792 an ideal choice for amplifying low level signals from high impedance capacitive transducers. 100% Tested Low Voltage Noise: 6nV/√Hz Max A Grade 100% Temperature Tested Voltage Gain: 1.
PAGE 2
LT1792 W W W AXI U U ABSOLUTE RATI GS (Note 1) Supply Voltage ..................................................... ±20V Differential Input Voltage ...................................... ±40V Input Voltage (Equal to Supply Voltage) ............... ±20V Output Short-Circuit Duration ........................ Indefinite Operating Temperature Range ............... – 40°C to 85°C Specified Temperature Range Commercial (Note 8) ......................... – 40°C to 85°C Industrial ..........................
PAGE 3
LT1792 ELECTRICAL CHARACTERISTICS TA = 25°C, VS = ±15V, VCM = 0V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS LT1792AC/LT1792AI MIN TYP MAX LT1792C/LT1792I MIN TYP MAX AVOL Large-Signal Voltage Gain VO = ±12V, RL = 10k VO = ±10V, RL = 1k 1200 600 4800 4000 1000 500 4500 3000 V/mV V/mV VOUT Output Voltage Swing RL = 10k RL = 1k ±13.0 ±12.0 ±13.2 ±12.3 ±13.0 ±12.0 ±13.2 ±12.3 V V SR Slew Rate RL ≥ 2k (Note 7) 2.3 3.4 2.3 3.
PAGE 4
LT1792 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the temperature range – 40°C ≤ TA ≤ 85°C. VS = ±15V, VCM = 0V, unless otherwise noted. (Notes 8, 9) LT1792AC/LT1792AI MIN TYP MAX LT1792C/LT1792I MIN TYP MAX VS = ±5V ● ● 0.5 0.8 1.0 1.4 1.2 1.5 3.7 4.2 mV mV (Note 6) ● 4 10 7 40 µV/°C Input Offset Current ● 300 800 300 800 pA IB Input Bias Current ● 1200 4000 1200 4000 pA VCM Input Voltage Range ● ● 12.6 –10.0 13.0 –10.5 12.6 –10.0 13.
PAGE 5
LT1792 U W TYPICAL PERFOR A CE CHARACTERISTICS Voltage Noise vs Chip Temperature Voltage Noise vs Frequency VOLTAGE NOISE (1µV/DIV) RMS VOLTAGE NOISE DENSITY (nV/√Hz) 100 10 VS = ±15V TA = 25°C 9 VOLTAGE NOISE (AT 1kHz) (nV/√Hz) 0.1Hz to 10Hz Voltage Noise 10 1/f CORNER 30Hz 8 7 6 5 4 3 2 1 1 2 0 6 4 TIME (SEC) 8 1 10 10 100 1k FREQUENCY (Hz) 300 200 BIAS CURRENT 100 OFFSET CURRENT V+ VS = ±15V 30 10 3 1 IB 0.3 IOS 0.1 0.03 100 125 1792 G22 60 40 20 0 100k 1M FREQUENCY (Hz) 4.
PAGE 6
LT1792 U W TYPICAL PERFOR A CE CHARACTERISTICS Gain and Phase Shift vs Frequency TA = 25°C VS = ±15V CL = 10pF 100 120 30 140 20 GAIN 10 160 0 180 1 10 FREQUENCY (MHz) 0.1 AV = 1 CL = 10pF VS = ±15V, ±5V 200 100 –10 5V/DIV PHASE PHASE SHIFT (DEG) VOLTAGE GAIN (dB) 40 Large-Signal Transient Response Small-Signal Transient Response 80 20mV/DIV 50 1µs/DIV 1792 G10 AV = 1 CL = 10pF RL = 2k VS = ±15V 1792 G11 5µs/DIV 1792 G09 Output Voltage Swing vs Load Current 40 –55°C – 1.4 –1.
PAGE 7
LT1792 U W TYPICAL PERFOR A CE CHARACTERISTICS THD and Noise vs Output Amplitude for Inverting Gain 1 TOTAL HARMONIC DISTORTION + NOISE (%) TOTAL HARMONIC DISTORTION + NOISE (%) THD and Noise vs Output Amplitude for Noninverting Gain ZL = 2k  15pF, fO = 1kHz AV = 1, 10, 100 MEASUREMENT BANDWIDTH = 10Hz TO 22kHz 0.1 AV = 100 0.01 AV = 10 0.001 AV = 1 0.0001 0.3 1 10 OUTPUT SWING (VP-P) 1 ZL = 2k  15pF, fO = 1kHz AV = – 1, – 10, – 100 MEASUREMENT BANDWIDTH = 10Hz TO 22kHz 0.1 AV = –100 0.
PAGE 8
LT1792 U W U UO S I FOR ATIO APPLICATI 1k best bipolar op amps, with higher current noise, will eventually lose out to the LT1792 when transducer impedance increases. The low voltage noise of the LT1792 allows it to surpass most single JFET op amps available. For the best performance versus area available anywhere, the LT1792 is offered in the SO-8 surface mount package with no degradation in performance.
PAGE 9
LT1792 W U U UO APPLICATI S I FOR ATIO the input of the LT1792. The charge across the transducer capacitance, CS, is transferred to the feedback capacitor CF, resulting in a change in voltage, dV, equal to dQ/CF. The gain therefore is CF/CS. For unity gain, the CF should equal the transducer capacitance plus the input capacitance of the LT1792 and RF should equal RS.
PAGE 10
LT1792 W U U UO APPLICATI S I FOR ATIO CF also increases the parasitic gate capacitance, which if left unchecked, can result in increased overshoot and ringing. When the feedback around the op amp is resistive (RF), a pole will be created with RF, the source resistance and capacitance (RS, CS), and the amplifier input capacitance (CIN = 27pF). In low gain configurations and with RS and RF in the kilohm range (Figure 5), this pole can create excess phase shift and even oscillation.
PAGE 11
LT1792 UO TYPICAL APPLICATI S Low Noise Light Sensor with DC Servo C1 2pF R1 1M 2 – 3 + 6 LT1792 OUTPUT C2 0.
PAGE 12
LT1792 UO TYPICAL APPLICATI S Light Balance Detection Circuit I1 Unity-Gain Buffer with Extended Load Capacitance Drive Capability R1 1M R2 1k C1 2pF TO 8pF C1 – PD1 – I2 VOUT LT1792 + + VIN VOUT LT1792 PD2 R1 33Ω CL 1792 TA08 C1 = CL ≤ 0.1µF OUTPUT SHORT-CIRCUIT CURRENT (∼ 30mA) WILL LIMIT THE RATE AT WHICH THE VOLTAGE CAN CHANGE ACROSS LARGE CAPACITORS 1792 TA07 VOUT = 1M × (I1 – I2) PD1,PD2 = HAMAMATSU S1336-5BK WHEN EQUAL LIGHT ENTERS PHOTODIODES, VOUT < 3mV.