Datasheet

LT1965 Series
17
1965fb
For more information www.linear.com/LT1965
typical applications
Paralleling of Regulators for Higher Output Current
package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
R1
0.01Ω
R2
0.01Ω
R5
10k
R4
2.2k
R7
4.02k
1%
C2
22µF
1965 TA03
V
IN
> 3.7V
3.3V
2.2A
8
1
3
2
4
C3
0.01µF
IN OUT
SENSE
GND
LT1965-3.3
SHDN
IN
SHDN
OUT
ADJ
GND
LT1965
SHDN
+
C1
100µF
+
–
+
1/2
LT1366
R6
6.65k
1%
R3
2.2k
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 0509 REV C
0.25 ±0.05
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.65 ±0.05
(2 SIDES)2.10 ±0.05
0.50
BSC
0.70 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)