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LT3071

3071fb

For more information www.linear.com/3071

ApplicAtions

FPGA and DSP Supplies

ASIC and Microprocessor Supplies

Servers and Storage Devices

Post Buck Regulation and Supply Isolation

typicAl ApplicAtion

Description

5A, Low Noise,

Programmable Output, 85mV

Dropout Linear Regulator

with Analog Margining

The LT

3071 is a low voltage, UltraFast™ transient re-

sponse linear regulator. The device supplies up to 5A of

output current with a typical dropout voltage of 85mV.

A 0.01µF reference bypass capacitor decreases output

voltage noise to 25µV

RMS

. The LT3071’s high bandwidth

permits the use of low ESR ceramic capacitors, saving

bulk capacitance and cost. The LT3071’s features make

it ideal for high performance FPGAs, microprocessors or

sensitive communication supply applications.

Output voltage is digitally selectable in 50mV increments

over a 0.8V to 1.8V range. An analog margining function

allows the user to adjust system output voltage over a

continuous ±10% range. The IC incorporates a unique

tracking function to control a buck regulator powering

the LT3071’s input. This tracking function drives the buck

regulator to maintain the LT3071’s input voltage to V

OUT

+ 300mV, minimizing power dissipation.

Internal protection includes UVLO, reverse-current protec-

tion, precision current limiting with power foldback and

thermal shutdown. The LT3071 regulator is available in a

thermally enhanced 28-lead, 4mm × 5mm QFN package.

0.9V, 5A Regulator

FeAtures

Output Current: 5A

Dropout Voltage: 85mV Typical

Digitally Programmable V

OUT

: 0.8V to 1.8V

Analog Output Margining: ±10% Range

Low Output Noise: 25µV

RMS

(10Hz to 100kHz)

Parallel Multiple Devices for 10A or More

Precision Current Limit: ±20%

Output Current Monitor: I

MON

= I

OUT

/2500

±1% Accuracy Over Line, Load and Temperature

Stable with Low ESR Ceramic Output Capacitors

(15µF Minimum)

High Frequency PSRR: 30dB at 1MHz

Enable Function Turns Output On/Off

VIOC Pin Controls Buck Converter to Maintain Low

Power Dissipation and Optimize Efficiency

PWRGD/UVLO/Thermal Shutdown Flag

Current Limit with Foldback Protection

Thermal Shutdown

28-Lead (4mm × 5mm × 0.75mm) QFN Package

Dropout Voltage

L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. UltraFast and VLDO are trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Patents pending.

OUTPUT CURRENT (A)

DROPOUT VOLTAGE (mV)

120

150

3071 TA01b

OUT

= 1.8V

BIAS

= 3.3V

OUT

= 0.8V

BIAS

= 2.5V

= V

OUT(NOMINAL)

BIAS

50k

LT3071

330µF

2.2µF

2.2µF*

0.01µF

*X5R OR X7R CAPACITORS

1nF

4.7µF*

3071 TA01a

10µF*

PWRGD

OUT

0.9V

MON

2V AT 5A

FULL SCALE

MARGA

VIOC

SENSE

OUT

BIAS

2.2V TO 3.6V

1.2V

PWRGD

REF/BYP

MON

GND

Summary of content (28 pages)

PAGE 1
LT3071 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining Features n n n n n n n n n n n n n n n n n Description Output Current: 5A Dropout Voltage: 85mV Typical Digitally Programmable VOUT : 0.8V to 1.
PAGE 2
LT3071 VO0 VO1 VO2 GND BIAS TOP VIEW EN 28 27 26 25 24 23 VIOC 1 22 MARGA PWRGD 2 21 IMON REF/BYP 3 20 GND GND 4 19 SENSE 29 GND IN 5 18 OUT IN 6 17 OUT IN 7 16 OUT IN 8 15 OUT GND GND GND 9 10 11 12 13 14 GND IN, OUT...................................................... –0.3V to 3.3V BIAS.............................................................. –0.3V to 4V VO2, VO1, VO0 Inputs..................................... –0.3V to 4V MARGA Input.......................................
PAGE 3
LT3071 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. PARAMETER CONDITIONS Regulated Output Voltage Margining (Note 3) MARGA = 1.2V MARGA = 0V l l MIN TYP MAX UNITS 9.5 –10.5 10 –10 10.5 –9.5 % % Line Regulation to VIN VOUT = 0.8V, ∆VIN = 1.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA VOUT = 1.
PAGE 4
LT3071 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. PARAMETER CONDITIONS MIN VIZ Input Range (Logic-Z State), VO2, VO1, VO0 VIH Input Threshold (Logic-1 State), VO2, VO1, VO0 Input Rising l 0.75 l VBIAS – 0.25 Input Hysteresis (Both Thresholds), VO2, VO1, VO0 TYP MAX VBIAS – 0.
PAGE 5
LT3071 Typical Performance Characteristics Dropout Voltage vs IOUT Dropout Voltage vs Temperature VIN = VOUT(NOMINAL) TJ = 25°C 25 120 VOUT = 1.8V VBIAS = 3.3V 60 VOUT = 0.8V VBIAS = 2.5V 30 0 VIN = VOUT(NOMINAL) IOUT = 1A 20 15 10 VOUT = 1.8V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V VOUT = 1.2V, VBIAS = 3.3V 5 0 1 3 4 2 OUTPUT CURRENT (A) 90 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 5 Dropout Voltage vs Temperature 60 30 VOUT = 1.8V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.
PAGE 6
LT3071 Typical Performance Characteristics Output Voltage (1.8V) vs Temperature 3.0 ILOAD = 10mA 1.814 GND PIN CURRENT (mA) 1.802 1.798 1.794 1.790 2.0 1.5 1.0 VOUT = 1.8V, VBIAS = 3.3V VOUT = 1.2V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V 0.5 1.786 0 1.782 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 0 1 3071 G10 10 VBIAS = 2.5V 350 VEN = 0V BIAS Pin Undervoltage Lockout Threshold 300 250 200 150 100 50 2.
PAGE 7
LT3071 Typical Performance Characteristics 4.0 VBIAS = 2.5V 1.4 1.2 1.0 0.8 EN PIN RISING EN PIN FALLING 0.6 0.4 0.2 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) Logic Input Threshold Voltages Logic Hi-Z to High State Transitions 2.8 INPUT RISING LOGIC Hi-Z TO HIGH 2.7 INPUT FALLING LOGIC HIGH TO Hi-Z 2.6 6.0 3 3.5 BIAS VOLTAGE (V) 0.6 0.5 5.5 3071 G16b 0.4 3071 G18 Logic Pin Input Current, High State 40 VEN = VBIAS = 2.5V 4.5 4.0 3.5 3.0 2.
PAGE 8
LT3071 Typical Performance Characteristics VIN = VOUT(NOMINAL) + 300mV 7.25 6.75 CURRENT LIMIT (A) CURRENT LIMIT (A) 7.00 6.50 6.25 6.00 5.75 6 5 4 3 VOUT = 1.8V VOUT = 1.2V VOUT = 0.8V 1 5.00 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 0 IN Pin Ripple Rejection 60 50 40 30 20 70 3.8 50 40 COUT = 117µF COUT = 16.9µF VOUT = 1V VIN = 1.3V + 50mVP-P RIPPLE VBIAS = 2.5V IOUT = 1A 10 0 10 100 1k 10k 100k FREQUENCY (Hz) 60 50 40 COUT = 117µF COUT = 16.
PAGE 9
LT3071 Typical Performance Characteristics Bias Voltage Line Regulation Bias Voltage Line Regulation 500 400 300 200 100 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) VBIAS = 3.25V TO 3.6V 300 VIN = 2.1V VOUT = 1.8V 200 IOUT = 10mA 100 0 –100 –200 –300 –400 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G33 150 100 50 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 16 14 12 8 6 4 2 0 0.1 0.3 0.4 0.2 REF/BYP CAPACITANCE (µF) 0 80 70 0.
PAGE 10
LT3071 Typical Performance Characteristics Bias Voltage Line Transient Response Input Voltage Line Transient Response VIOC Amplifier IN-to-OUT Servo Voltage VOUT 10mV/DIV VOUT 1mV/DIV VIN 50mV/DIV VBIAS 200mV/DIV VIN = 1.3V VOUT = 1V IOUT = 5A COUT = 16.9µF 20µs/DIV 3071 G42 VIN = 1.3V VBIAS = 2.5V VOUT = 1V IOUT = 5A COUT = 16.9µF 3071 G43 20µs/DIV VIOC IN-TO-OUT SERVO VOLTAGE (mV) 350 340 VBIAS = 2.
PAGE 11
LT3071 Pin Functions VIOC (Pin 1): Voltage for In-to-Out Control. The IC incorporates a unique tracking function to control a buck regulator powering the LT3071’s input. The VIOC pin is the output of this tracking function that drives the buck regulator to maintain the LT3071’s input voltage at VOUT + 300mV. This function maximizes efficiency and minimizes power dissipation. See the Applications Information section for more information on proper control of the buck regulator. PWRGD (Pin 2): Power Good.
PAGE 12
LT3071 Pin Functions IMON (Pin 21): Output Current Monitor. The IMON pin sources a current typically equal to IOUT/2500 or 400µA per amp of output current. Terminating this pin with a resistor to GND produces a voltage proportional to IOUT . For example, at IOUT = 5A, IMON typically sources 2mA. With a 1k resistor to GND, this produces 2V. If IMON is unused, tie this pin to VBIAS. Applications Information section that defines the VO2, VO1 and VO0 settings versus VOUT . BIAS (Pin 27): Bias Supply.
PAGE 13
LT3071 Block Diagram 27 BIAS IN 5-8 UVLO AND THERMAL SHUTDOWN + + IMON ISENSE REF/BYP – + 21 – EAMP BUF – OUT 15-18 LDO CORE SENSE PWRGD DETECT + – 1 VIOC 19 2 VOUT(NOM) + 300mV REF/BYP VREF GND 4,9-14,20,26,29 600mV 3 PROGRAM CONTROL EN 28 VO2 25 VO1 24 VO0 MARGA 23 22 LOGIC HIGH STATE 28 VBIAS – 0.25V EN 500k TO INTERNAL ENABLE (SEE ENABLE THRESHOLD CURVE) – + LOGIC HIGH STATE VBIAS 100k VBIAS – 0.9V 100k 0.75V VO2, VO1, VO0 + – + – HIGH IF IN > VBIAS – 0.
PAGE 14
LT3071 Applications Information Introduction Current generation FPGA and ASIC processors place stringent demands on the power supplies that power the core, I/O and transceiver channels. These microprocessors may cycle load current from near zero to amps in tens of nanoseconds. Output voltage specifications, especially in the 1V range, require tight tolerances including transient response as part of the requirement.
PAGE 15
LT3071 Applications Information FPGA and ASIC processors are sufficient to stabilize the system (see Stability and Output Capacitance section). This regulator design provides ample bandwidth and responds to transient load changes in a few hundred nanoseconds versus regulators that respond in many microseconds. The LT3071 also incorporates precision current limiting, enable/disable control of output voltage and integrated overvoltage and thermal shutdown protection.
PAGE 16
LT3071 Applications Information Output Voltage Margining The LT3071’s analog margining pin, MARGA, provides a continuous output voltage adjustment range of ±10%. It margins VOUT by adjusting the internal 600mV reference voltage up and down. The MARGA pin’s typical input impedance is 190kΩ between MARGA and the internal VREF node. Driving MARGA with 600mV to 1.2V provides 0% to 10% of adjustment. Driving MARGA with 600mV to 0V provides 0% to –10% of adjustment.
PAGE 17
LT3071 Applications Information IN LT3071 OUT SWITCHING REGULATOR REF + – LOAD PWM FB VOUT + VREF 300mV VIOC REFERENCE ITH 3071 F02 Figure 2. VIOC Control Block Diagram PWRGD—Power Good PWRGD pin is an open-drain NMOS digital output that actively pulls low if any one of these fault modes is detected: • VOUT is less than 90% of VOUT(NOMINAL) on the rising edge of VOUT . • VOUT drops below 85% of VOUT(NOMINAL) for more than 25µs. • VBIAS is less than its undervoltage lockout threshold.
PAGE 18
LT3071 Applications Information Typical 0603 or 0805 case-size capacitors have an ESL of ~800pH and PCB mounting can contribute up to ~200pH. Thus, it becomes necessary to reduce the parasitic inductance by using a parallel capacitor combination. A suitable methodology must control this paralleling as capacitors with the same self-resonant frequency, fR, will form a tank circuit that can induce ringing of their own accord.
PAGE 19
LT3071 Applications Information 20 0 20 X5R CHANGE IN VALUE (%) CHANGE IN VALUE (%) 40 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF –20 –40 –60 Y5V –80 –100 0 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF X5R –20 –40 Y5V –60 –80 0 2 10 12 4 8 6 DC BIAS VOLTAGE (V) 14 16 –100 –50 –25 3071 F04 50 25 75 0 TEMPERATURE (°C) 100 125 3071 F05 Figure 4. Ceramic Capacitor DC Bias Characteristics Figure 5.
PAGE 20
LT3071 Applications Information wires. The most effective way to reduce overall inductance is to place the forward and return-current conductors (the wire for the input and the wire for the return ground) in very close proximity. Two 18-AWG wires separated by 0.05 inch reduce the overall self inductance to about onefourth of a single isolated wire.
PAGE 21
LT3071 Applications Information Reverse Voltage The LT3071 incorporates a circuit that detects if VIN decreases below VOUT . This reverse-voltage detector has a typical threshold of about (VIN – VOUT) = –6mV. If the threshold is exceeded, this detector circuit turns off the drive to the internal NMOS pass transistor, thereby turning off the output. The output pulls low with the load current discharging the output capacitance.
PAGE 22
LT3071 Applications Information Calculating Junction Temperature Paralleling Devices for Higher IOUT Example: Given an output voltage of 0.9V, an input voltage range of 1.2V ± 5%, a BIAS voltage of 2.5V, a maximum output current of 4A and a maximum ambient temperature of 50°C, what will the maximum junction temperature be? Multiple LT3071s may be paralleled to obtain higher output current. This paralleling concept borrows from the scheme employed by the LT3080.
PAGE 23
LT3071 Applications Information Quieting the Noise The LT3071 offers numerous noise performance advantages. Each LDO has several sources of noise. An LDO’s most critical noise source is the reference, followed by the LDO error amplifier. Traditional low noise regulators buffer the voltage reference out to an external pin (usually through a large value resistor) to allow for bypassing and noise reduction of reference noise.
PAGE 24
LT3071 Typical Applications VBIAS 3.3V 47µF 6.3V ×3 1Ω 50k SVIN NC 0.1µF PGOOD RUN PVIN PVIN SVIN TRACK SW PVIN SW PVIN SW PLLLPF SW NC VFB PGND CLKIN NC VO0 NC VO1 VO2 ITH BSEL PHMODE IN 20k 100µF 6.3V ×2 SVIN NC 4.7nF VOUT 1V 5A 10µF* OUT 2.2µF* 4.7µF* *X5R OR X7R CAPACITORS MARGA 2k PWRGD SENSE LT3071 VIOC 10k ITHM MODE BIAS EN 1.3V/5A 47µF MGN CLKOUT NC 0.2µH SGND LTC3415EUHF NC PWRGD 2.2µF VMON 2V AT 5A FULL SCALE IMON REF/BYP GND 1k 0.
PAGE 25
LT3071 Typical Applications 50k VIN 3.3V BIAS EN IN 47µF NC NC PWRGD SENSE VO0 LT3071 NC 2.2µF* VO1 1nF VIN 3.3V NC 10µF NC NC NC SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2 VOUT1 VIN1 SVIN1 MGN1 FB1 RUN1 ITH1 PLLLPF1 ITHM1 MODE1 BSEL1 PHMODE1 PGOOD1 TRACK1 VOUT2 VIN2 MGN2 SVIN2 FB2 RUN2 ITH2 PLLLPF2 ITHM2 MODE2 BSEL2 PHMODE2 PGOOD2 TRACK2 SW2 SGND1 GND1 SGND2 GND2 RTRACE 2.5mΩ CONTROLLED IMON REF/BYP GND P.O.L. 1 0.01µF POWER PLANE 1V/7A P.O.L. 2 2.2µF 100µF 6.
PAGE 26
LT3071 Package Description UFD Package 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 ±0.05 4.50 ± 0.05 3.10 ± 0.05 2.50 REF 2.65 ± 0.05 3.65 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.50 REF 4.10 ± 0.05 5.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 (2 SIDES) R = 0.05 TYP 0.75 ± 0.05 PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 2.50 REF R = 0.115 TYP 27 28 0.40 ± 0.
PAGE 27
LT3071 Revision History REV DATE DESCRIPTION PAGE NUMBER A 8/10 Swapped IN and EN pins in Figure 7 24 B 4/13 Clarified parameters, conditions and notes in Electrical Characteristics table 3, 4 Added new graph: EN Pin Threshold and Hysteresis vs VBIAS 7 Clarified EN pin operation 12 Enhanced Block Diagram 13 3071fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 28
LT3071 Typical Application 1.5V to 1.2V Linear Regulator 50k VBIAS 2.2V TO 3.6V PWRGD 2.2µF VIN 1.5V IN EN 330µF VO0 BIAS PWRGD SENSE LT3071 OUT VO1 2.2µF* VO2 NC 1nF MARGA VIOC IMON REF/BYP GND 4.7µF* *X5R OR X7R CAPACITORS 0.01µF 10µF* VOUT 1.2V 5A VMON 2V AT 5A FULL SCALE 1k 3071 TA02 Related Parts PART DESCRIPTION COMMENTS LT1764/LT1764A 3A, Fast Transient Response, Low Noise LDO 340mV Dropout Voltage, Low Noise: 40µVRMS, VIN: 2.