Datasheet

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LT3581

3581fa

For more information www.linear.com/LT3581

Typical applicaTion

DescripTion

3.3A Boost/Inverting DC/DC

Converter with Fault Protection

The LT

3581 is a PWM DC/DC converter with built-in fault

protection features to aid in protecting against output

shorts, input/output overvoltages, and overtemperature

conditions. The part consists of a 42V master switch, and

a 42V slave switch that can be tied together for a total

current limit of 3.3A.

The LT3581 is ideal for many local power supply designs. It

can be easily configured in Boost, SEPIC, Inverting or Flyback

configurations, and is capable of generating 12V at 830mA,

or –12V at 625mA from a 5V input. In addition, the LT3581’s

slave switch allows the part to be configured in high voltage,

high power charge pump topologies that are very efficient

and require fewer components than traditional circuits.

The LT3581’s switching frequency range can be set bet ween

200kHz and 2.5MHz. The part may be clocked internally at

a frequency set by the resistor from the RT pin to ground,

or it may be synchronized to an external clock. A buffered

version of the clock signal is driven out of the CLKOUT

pin, and may be used to synchronize other compatible

switching regulator ICs to the LT3581.

The LT3581 also features innovative SHDN pin circuitry that

allows for slowly varying input signals and an adjustable

undervoltage lockout function. Additional features such

as frequency foldback and soft-start are integrated. The

LT3581 is available in 14-Pin 4mm × 3mm DFN and 16-

Lead MSE packages.

Output Short Protected, 5V to 12V Boost Converter Operating at 2MHz

FeaTures

applicaTions

3.3A, 42V Combined Power Switch

Master/Slave (1.9A/1.4A) Switch Design

Output Short Circuit Protection

Wide Input Range: 2.5V to 22V Operating,

40V Maximum Transient

Switching Frequency Up to 2.5MHz

Easily Configurable as a Boost, SEPIC, Inverting or

Flyback Converter

User Configurable Undervoltage Lockout

Low V

CESAT

Switch: 250mV at 2.75A (Typical)

Can be Synchronized to External Clock

Can Be Synchronized to other Switching Regulators

High Gain SHDN Pin Accepts Slowly Varying Input

Signals

14-Pin 4mm × 3mm DFN and 16-Lead MSE Packages

Local Power Supply

Vacuum Fluorescent Display (VFD) Bias Supplies

TFT-LCD Bias Supplies

Automotive Engine Control Unit (ECU) Power

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 7579816.

6.04k

100k

130k

43.2k

4.7µF

1.5µH

1nF

3581 TA01

0.1µF

4.7µF

10.5k

4.7µF

OUT

12V

830mA

SW1 SW2

CLKOUT

GATE

GND

SYNC

FAULT

SHDN

LT3581

56pF

18.7k

10k

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

400

100

3581 TA01b

200 1000800600

200

600

2000

1200

1400

1600

1800

400

800

1000

Efficiency and Power Loss vs

Load Current

Summary of content (36 pages)

PAGE 1
LT3581 3.3A Boost/Inverting DC/DC Converter with Fault Protection Features n n n n n n n n n n n n Description 3.3A, 42V Combined Power Switch Master/Slave (1.9A/1.4A) Switch Design Output Short Circuit Protection Wide Input Range: 2.5V to 22V Operating, 40V Maximum Transient Switching Frequency Up to 2.5MHz Easily Configurable as a Boost, SEPIC, Inverting or Flyback Converter User Configurable Undervoltage Lockout Low VCESAT Switch: 250mV at 2.
PAGE 2
LT3581 Absolute Maximum Ratings (Note 1) VIN Voltage.................................................. –0.3V to 40V SW1/SW2 Voltage ...................................... –0.4V to 42V RT Voltage.................................................... –0.3V to 5V SS, FB Voltage........................................... –0.3V to 2.5V VC Voltage..................................................... –0.3V to 2V SHDN Voltage............................................. –0.3V to 40V SYNC Voltage.....................
PAGE 3
LT3581 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN, unless otherwise noted. (Note 2). PARAMETER CONDITIONS Minimum Input Voltage MIN TYP MAX 2.3 2.5 V 22.1 23.5 25 V V l VIN Overvoltage Lockout UNITS Positive Feedback Voltage l 1.195 1.215 1.
PAGE 4
LT3581 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN, unless otherwise noted. (Note 2). PARAMETER CONDITIONS MIN TYP MAX UNITS Soft-Start Charge Current VSS = 30mV, Current Flows Out of SS pin l 5.7 8.7 11.3 µA Soft-Start Discharge Current Part in FAULT, VSS = 2.1V, Current Flows into SS Pin l 5.7 8.7 11.
PAGE 5
LT3581 Typical Performance Characteristics Switch Fault Current Limit vs Duty Cycle Switch Saturation Voltage with SW1 and SW2 Tied Together 4 3 2 450 100 400 90 350 300 250 200 150 100 1 50 0 20 60 50 40 DUTY CYCLE (%) 30 70 0 80 0 1 2 3 4 SW1 + SW2 CURRENT (A) 3581 G01 Switch Fault Current Limit vs Temperature 80 70 60 50 40 30 20 10 0 5 0 1 2 4 3 SW1 + SW2 CURRENT (A) 3581 G02 Positive Feedback Voltage vs Temperature 6 5 3581 G03 CLKOUT Duty Cycle vs Temperature 1.
PAGE 6
LT3581 Typical Performance Characteristics TA = 25°C, unless otherwise noted. Commanded Current Limit vs SS Voltage Gate Current vs SS Voltage 1000 SHDN Voltage Threshold with Hysteresis 1.40 5 1.38 900 700 600 500 400 300 200 4 1.36 SHDN VOLTAGE (V) SW1 + SW2 CURRENT (A) GATE CURRENT (µA) 800 3 2 SHDN FALLING 1.28 1.26 0 1.20 –50 –25 1.22 0.25 0.50 0.75 1.00 SS VOLTAGE (V) 1.25 1.50 0 0.2 0.4 0.6 0.
PAGE 7
LT3581 Pin Functions (DFN/MSOP) FB (Pin 1/Pin 1): Positive and Negative Feedback Pin. For a Boost or Inverting Converter, tie a resistor from the FB pin to VOUT according to the following equations: – 1.215V  V RFB =  OUT ; Boost or SEPIC Converter  83.3 • 10 –6   | V | + 9mV  RFB =  OUT ; Inverting Converter  83.3 • 10 –6  VC (Pin 2/Pin 2): Error Amplifier Output Pin. Tie external compensation network to this pin. GATE (Pin 3/Pin 3): PMOS Gate Drive Pin.
PAGE 8
LT3581 Block Diagram VIN CIN OPTIONAL D1 L1 M1 COUT1 RFAULT DIE TEMP 165°C 2.1V + – – + 1.8V 250k 750mV STARTUP AND FAULT LOGIC LDO SS VIN ** + – + – SW2 ** + – ISW1 + – + – VC 22V MIN – + 933µA 50mV RGATE FAULT GATE SOFTSTART VOUT COUT2 DRIVER DISABLE CSS SW1 42V MIN SAMPLE MODE BLOCK 42V MIN + – FB 1.9A MIN TD ~ 30ns SAMPLE SHDN 1.33V + – + – + – SW2 45mV VBE • 0.9 RFB Q2 SW1 COMPARATOR SR1 – UVLO VIN 1.17V R A3 A3 1.
PAGE 9
LT3581 State Diagram SHDN < 1.33V (TYPICAL) or VIN < 2.3V (TYPICAL) CHIP OFF • ALL SWITCHES DISABLED • IGATE OFF • FAULTS CLEARED SHDN > 1.33V (TYPICAL) AND VIN > 2.3V (TYPICAL) INITIALIZE • SS PULLED LOW FAULT1 FAULT2 FAULT DETECTED SS < 50mV SOFT START • IGATE ENABLED • SS CHARGES UP • SWITCHER ENABLED FAULT1 • SS CHARGES UP • IGATE OFF • FAULT PIN PULLED LOW INTERNALLY BY LT3581 • SWITCHER DISABLED • CLKOUT DISABLED SS > 1.
PAGE 10
LT3581 Operation Operation – Overview The LT3581 uses a constant-frequency, current mode control scheme to provide excellent line and load regulation. The part’s undervoltage lockout (UVLO) function, together with soft-start and frequency foldback, offers a controlled means of starting up. Fault features are incorporated in the LT3581 to aid in the detection of output shorts, over-voltage, and overtemperature conditions.
PAGE 11
LT3581 Operation Sample Mode Sample Mode is the mechanism used by the LT3581 to aid in the detection of output shorts. It refers to a state of the LT3581 where the master and slave power switches (Q1 and Q2) are turned on for a minimum period of time every clock cycle (or every few clock cycles in frequency foldback) in order to “sample” the inductor current. If the sampled current through Q1 exceeds the master switch current limit of 1.
PAGE 12
LT3581 Operation Refer to the State Diagram (Figure 2) for the following description of the LT3581’s operation during a fault event. When a fault is detected, in addition to the FAULT pin being pulled low internally, the LT3581 also disables its CLKOUT pin, turns off its power switches, and the GATE pin becomes high impedance. The external PMOS, M1, turns off when the gate of M1 is pulled up to its source by the external RGATE resistor (see Block Diagram).
PAGE 13
LT3581 Applications Information Boost Converter Component Selection D1 20V, 2A L1 1.5µH VIN 5V CIN 4.7µF RFAULT 100k RT 43.2k VIN FB LT3581 FAULT GATE SHDN CLKOUT RT VC SYNC SS GND PARAMETERS/EQUATIONS OPTIONAL PMOS COUT1 4.7µF SW1 SW2 Table 1. Boost Design Equations RGATE 6.04k VOUT 12V IOUT < 0.83A Step 1: Pick VIN, VOUT, and fOSC to calculate equations below. Inputs Step 2: DC RFB 130k DC ≅ COUT2 4.7µF CF 56pF CSS 0.1µF L TYP = RC 10.
PAGE 14
LT3581 Applications Information SEPIC Converter Component Selection (Coupled or Un-Coupled Inductors) C1 1µF L1 3.3µH CIN 22µF RFAULT 100k ENABLE RT 124k SW1 SW2 VIN • L2 3.3µH PARAMETERS/EQUATIONS Step 1: Inputs D1 30V, 2A • VIN 3V TO 16V Table 2. SEPIC Design Equations COUT 22µF ×2 RFB 45.3k VOUT 5V IOUT < 0.9A (VIN = 3V) IOUT < 1.5A (VIN = 12V) Pick VIN, VOUT, and fOSC to calculate equations below.
PAGE 15
LT3581 Applications Information Dual Inductor Inverting Converter Component Selection (Coupled or Un-Coupled Inductors) C1 1µF L1 3.3µH RFAULT 100k ENABLE RT 43.2k VOUT –12V IOUT < 625mA • CIN 3.3µF VIN COUT 4.7µF D1 20V 1A SW1 SW2 PARAMETERS/EQUATIONS Step 1: Inputs Pick VIN, VOUT, and fOSC to calculate equations below. L2 3.3µH • VIN 5V Table 3.
PAGE 16
LT3581 Applications Information Layout Guidelines for Boost, SEPIC, and Dual Inductor Inverting Topologies General Layout Guidelines • To optimize thermal performance, solder the exposed ground pad of the LT3581 to the ground plane, with multiple vias around the pad connecting to additional ground planes. • A ground plane should be used under the switcher circuitry to prevent interplane coupling and overall noise.
PAGE 17
LT3581 Applications Information GND 1 CIN A – VIN + SYNC 16 2 15 17 3 14 4 13 SHDN 5 12 CLKOUT 6 11 7 10 8 9 B GND C C1 COUT L1 • • D1 – VOUT L2 3581 F10 A: RETURN CIN GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD. B: RETURN COUT GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
PAGE 18
LT3581 Applications Information where TJ = Die Junction Temperature, TA = Ambient Temperature, PTOTAL is the final result from the calculations shown in Table 4, and θJA is the thermal resistance from the silicon junction to the ambient air. The published (http://www.linear.com/designtools/packaging/Linear_Technology_Thermal_Resistance_Table. pdf) θJA value is 43°C/W for the 4mm × 3mm 14-pin DFN package and 45°C/W for the 16-lead MSOP package.
PAGE 19
LT3581 Applications Information Clock Synchronization 2.2µF 1.5µH The operating frequency of the LT3581 can be set by an external source by simply providing a digital clock signal into the SYNC pin (RT resistor still required). The LT3581 will revert to its internal free-running oscillator clock (set by the RT resistor) when the SYNC pin is driven below 0.4V for a few free-running clock periods.
PAGE 20
LT3581 Applications Information • The slave switch, by not performing a current sense operation like the master switch, can sustain fairly large current spikes when the flying capacitors charge up. Since this current spike flows through SW2, it does not affect the operation of the current comparator (A4 in Block Diagram). • The master switch, immune from the capacitor current spike (seen only by the slave switch) can sense the inductor current more accurately.
PAGE 21
LT3581 Applications Information Hot-Plug The high inrush current associated with hot-plugging VIN can be largely rejected with the use of an external PMOS. A simple hot-plug controller can be designed by connecting an external PMOS in series with VIN, with the gate of the PMOS being driven by the GATE pin of the LT3581.
PAGE 22
LT3581 Appendix Setting the Output Voltage The output voltage is set by connecting a resistor (RFB) from VOUT to the FB pin. RFB is determined by using the following equation: RFB = | VOUT – VFB | 83.3µA Power Switch Duty Cycle In order to maintain loop stability and deliver adequate current to the load, the power NPNs (Q1 and Q2 in the Block Diagram) cannot remain “on” for 100% of each clock cycle.
PAGE 23
LT3581 appendix Minimum Inductance Although there can be a tradeoff with efficiency, it is often desirable to minimize board space by choosing smaller inductors. When choosing an inductor, there are three conditions that limit the minimum inductance: (1) providing adequate load current, (2) avoidance of subharmonic oscillations and (3) supplying a minimum ripple current to avoid false tripping of the current comparator.
PAGE 24
LT3581 appendix Inductor Current Rating Inductors must have a rating greater than their peak operating current, or else they could saturate and hence contribute to losses in efficiency.
PAGE 25
LT3581 appendix The use of the external PMOS, controlled by the GATE pin, is particularly beneficial when dealing with unintended output shorts in a boost regulator. In a conventional boost regulator, the inductor, Schottky diode, and power switches are susceptible to damage in the event of an output short to ground.
PAGE 26
LT3581 appendix found. Figures 15a to 15c illustrate this process for the circuit of Figure 18 with a load current stepped between 540mA and 800mA. Figure 15a shows the transient response with RC equal to 1k. The phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. In Figure 15b, the value of RC is increased to 3k, which results in a more damped response. Figure 15c shows the results when RC is increased further to 10.5k.
PAGE 27
LT3581 appendix From Figure 16, the DC gain, poles and zeros can be calculated as follows: DC Gain : (Breaking loop at FB pin) ∂V ∂I ∂V ∂V ADC = A OL (0) = C • VIN • OUT • FB = ∂VFB ∂VC ∂IVIN ∂VOUT   (gma • RO ) • gmp •  η • VVIN • R2L  • R 0+.50R.
PAGE 28
LT3581 Typical Applications L1 1.5µH VIN 5V D1 SW1 SW2 18.7k FB VIN 100k C1 4.7µF FAULT GATE SHDN CLKOUT RT 10k LT3581 SYNC 43.2k VOUT 12V 830mA M1 C2 4.7µF 6.04k D2 130k VIN VC 56pF SS GND C3 4.7µF 10.5k 0.1µF 1nF 3581 F18 C1: 4.7µF, 16V, X7R, 1206 C2, C3: 4.7µF, 25V, X7R, 1206 D1: DIODES INC. PD3S230H-7 D2: VISHAY MSS2P3 L1: SUMIDA CDR6D28MN-IR5 M1: VISHAY SILICONIX SI7123DN Figure 18.
PAGE 29
LT3581 Typical Applications High Efficiency, VFD (Vacuum Fluorescent Display) Power Supply Switches at 2MHz to Avoid AM Band DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY D6 C7 2.2µF D5 C5 2.2µF D4 C6 2.2µF D3 C4 2.2µF D2 D7 L1 10µH VIN 9V TO 16V C1 2.2µF 32.6k D1 FB 100k FAULT GATE SHDN CLKOUT RT 10k LT3581 SYNC 43.2k GND 365k 8.06k D9* 10V D8* VIN VC SS VOUT1 65V 60mA (VIN = 9V) 70mA (VIN = 12V) 90mA (VIN = 16V) M1* C2 2.
PAGE 30
LT3581 Typical Applications 2MHz, 12V SEPIC Converter Can Accept Input Voltages from 9V to 16V C2 2.2µF L1 3.3µH D1 VOUT 12V 1A (VIN = 9V) 1.1A (VIN = 12V) 1.3A (VIN = 16V) • VIN 9V TO 16V SW1 VIN C1 3.3µF 100k 43.2k • SW2 LT3581 L2 3.3µH FB SHDN GATE FAULT CLKOUT RT VC SYNC SS GND 130k C3 10µF 100pF 10k 0.1µF 2.2nF 3581 TA06a C1: 3.3µF, 25V, X7R, 1206 C2: 2.
PAGE 31
LT3581 Typical Applications Wide Input Range, 3.3V SEPIC Converter Can Operate from 3V to 36V D3 C4 2.2µF D2 VOUT 3.3V 0.9A (3V < VBAT < 9V) 1.5A (VBAT = 9V) • VBAT 3V TO 36V (VBAT AT START-UP = 6V TO 16V) L1 3.3µH C1 10µF 200k 10k SW1 M1 VIN 100k D1 18V C3 4.7µF C2 10nF 174k Q1 470pF SW2 LT3581 FB • 24.9k SHDN GATE FAULT VC RT SS 47pF CLKOUT GND 1µF SYNC L2 3.3µH C5 47µF ×2 10k 2.2nF 10k 3581 TA07a C1: 10µF, 50V, X7R, 1210 C2: 10nF, 25V, X7R, 0603 C3: 4.
PAGE 32
LT3581 Typical Applications 1MHz, ±12V Charge Pump Topology Uses Only Single Inductor D5 C5 10µF D4 VIN 5V C2 1µF D1 D3 C1 3.3µF 100k 86.6k SW2 LT3581 VIN FB SHDN GATE FAULT CLKOUT RT VC SYNC SS 1800 85 1600 130k 1200 75 1000 70 800 65 600 60 C4 10µF 100pF 16.9k 0.1µF 400 55 50 GND 1400 80 VOUT+ 12V 0.27A D2 SW1 90 POWER LOSS (mW) L1 8.2µH R1 *2.4k VOUT– –12V 0.
PAGE 33
LT3581 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MSE Package 16-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1667 Rev F) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ±0.102 (.112 ±.004) 5.10 (.201) MIN 2.845 ±0.102 (.112 ±.004) 0.889 ±0.127 (.035 ±.005) 8 1 1.651 ±0.102 (.065 ±.004) 1.651 ±0.102 3.20 – 3.45 (.065 ±.004) (.126 – .136) 0.305 ±0.038 (.0120 ±.0015) TYP 16 0.50 (.0197) BSC 4.039 ±0.102 (.159 ±.
PAGE 34
LT3581 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DE Package 14-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1708 Rev B) 4.00 ±0.10 (2 SIDES) R = 0.05 TYP 0.70 ±0.05 3.60 ±0.05 2.20 ±0.05 3.30 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 1.70 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF (DE14) DFN 0806 REV B 7 0.75 ±0.05 1 0.25 ± 0.05 0.50 BSC 3.00 REF 3.
PAGE 35
LT3581 Revision History REV DATE DESCRIPTION A 11/13 Added H-grade to Absolute Maximum Ratings table and Order Information table PAGE NUMBER 2 Clarified Electrical Characteristics 4 3581fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PAGE 36
LT3581 Typical Application 5V to –12V Inverting Converter Switches at 2MHz C2 1µF L1 3.3µH VOUT –12V 625mA • • VIN 5V Efficiency and Power Loss L2 3.3µH D1 SW1 SW2 100k 43.2k 85 1800 1600 80 FB SHDN GATE FAULT CLKOUT RT VC SYNC SS 143k C3 4.7µF 47pF GND 0.1µF 11k EFFICIENCY (%) C1 3.3µF LT3581 2000 1400 75 1200 70 1000 800 65 600 60 400 55 1nF 3581 TA05a 50 POWER LOSS (mW) VIN 90 200 0 C1: 3.3µF, 16V, X7R, 1206 C2: 1µF, 25V, X7R, 1206 C3: 4.