Datasheet

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LT4256-3

42563fa

The LT

4256-3 is a high voltage Hot Swap

controller that

allows a board to be safely inserted and removed from a

live backplane. An internal driver controls the high side

N-channel MOSFET gate for supply voltages ranging from

10.8V to 80V. The part features an open-circuit detect

(OPEN) output that indicates abnormally low load current

conditions.

The LT4256-3 also features an adjustable analog foldback

current limit. If the supply remains in current limit for more

than a programmable time, the N-channel MOSFET shuts

off, the PWRGD output asserts low and the LT4256-3

either automatically restarts after a time-out delay or

latches off until the UV pin is cycled low (depending on the

status of the RETRY pin).

The PWRGD output indicates when the output voltage

rises above a programmed level. An external resistor

string from V

provides programmable undervoltage and

overvoltage protection.

The LT4256-3 is available in a 16-lead SSOP package.

■

Hot Board Insertion

■

Electronic Circuit Breaker/Power Bussing

■

Industrial High Side Switch/Circuit Breaker

■

24V/48V Industrial/Alarm Systems

■

Ideally Suited for 12V, 24V and 48V Distributed

Power Systems

■

48V Telecom Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

Allows Safe Board Insertion and Removal from a

Live Backplane

■

Controls Supply Voltage from 10.8V to 80V

■

Foldback Current Limiting

■

Open Circuit and Overcurrent Fault Detect

■

Drives an External N-Channel MOSFET

■

Automatic Retry or Latched Off Operation

After Overcurrent Fault

■

Programmable Supply Voltage Power-Up Rate

■

Open MOSFET Detection

■

1% Over and Undervoltage Detection Accuracy

■

Available in a 16-Lead SSOP Package

Positive High Voltage

Hot Swap Controller

with Open-Circuit Detect

4256 TA01

0.020Ω

LT4256-3

SENSEV

GATE

OUT

PWRGD

RETRY

TIMER

GND

48V

GND

(SHORT PIN)

IRF540

CMPZ5241BS

11V

4.02k

64.9k

100Ω

4.02k

10Ω

36.5k

PWRGD

OUT

48V

51k

33nF

0.01µF

10nF

OPEN

SMAT70A

UV = 36V

OV = 73V

PWRGD = 40V

48V, 2A Hot Swap Controller

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

LT4256-3 Start-Up Behavior

Hot Swap is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

50V/DIV

OUT

50V/DIV

PWRGD

50V/DIV

2.5ms/DIV

= 225µF

42563 TA02

INRUSH

CURRENT

500mA/DIV

CONTACT BOUNCE

Summary of content (20 pages)

PAGE 1
LT4256-3 Positive High Voltage Hot Swap Controller with Open-Circuit Detect U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Allows Safe Board Insertion and Removal from a Live Backplane Controls Supply Voltage from 10.
PAGE 2
LT4256-3 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage (VCC) ................................ – 0.3 to 100V SENSE, PWRGD ....................................... – 0.3 to 100V GATE Voltage (Note 2) .................... – 0.3V to VCC + 10V GATE Maximum Current ..................................... 200µA VOUT .......................................................... –3V to 100V FB, UV, OPEN ............................................. – 0.3 to 44V OV ..........
PAGE 3
LT4256-3 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 48V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VFB FB Voltage Threshold FB High-to-Low Transition FB Low-to-High Transition VFBHYS FB Hysteresis Voltage VOLPGD PWRGD Output Low Voltage IO = 1.6mA IO = 5mA IPWRGD PWRGD Pin Leakage Current VPWRGD = 80V IINFB FB Input Current FB = 4.5V –0.
PAGE 4
LT4256-3 U W TYPICAL PERFOR A CE CHARACTERISTICS Specifications are at TA = 25°C unless otherwise noted. 0 63 60 –5 62 50 GATE PULL-DOWN CURRENT (mA) –15 –20 –25 32µA @ 25°C –30 –35 –40 –50 –25 0 25 50 TEMPERATURE (°C) 75 61 40 IGATE (mA ) –10 60 59 20 10 57 56 –50 100 0 –25 0 25 50 TEMPERATURE (°C) 75 100 VGATE – VOUT Voltage vs Temperature 6 VCC (V) 8 VCC = 18V 10 12 TIMER Currents vs Temperature 14.0 5.0 PULL-DOWN CURRENT 13.
PAGE 5
LT4256-3 U W TYPICAL PERFOR A CE CHARACTERISTICS Specifications are at TA = 25°C unless otherwise noted. UV Thresholds vs Temperature OV Current vs OV Voltage OV Thresholds vs Temperature 250 4.1 4.0 200 4.0 3.9 150 4.1 3.8 OV THRESHOLDS (V) IOV (µA) UV THRESHOLDS (V) L-H THRESHOLD 100 50 3.7 0 0 25 50 TEMPERATURE (°C) 75 0 100 5 10 VOV (V) 15 3.7 3.5 –50 20 5.0 9 4.5 6 5 4 3 2 1 75 100 PWRGD Output Voltage vs IPWRGD 6 5 4.0 3.
PAGE 6
LT4256-3 U U U PI FU CTIO S UV (Pin 1): Undervoltage Sense Input. UV is an input that enables the output voltage. When UV is driven above 4V, GATE will start charging and the output turns on. When UV goes below 3.6V, GATE discharges and the output shuts off. Pulsing UV to below 0.4V for at least 5µs after a current limit fault cycle resets the fault latch (when RETRY pin is low, commanding latch off operation) and allows the part to turn back on.
PAGE 7
LT4256-3 U U U PI FU CTIO S GATE (Pin 13): High Side Gate Drive for the External N-Channel MOSFET. An internal charge pump guarantees at least 10V of gate drive for VCC supply voltages above 20V and 4.5V of gate drive for VCC supply voltages between 10.8V and 20V. The rising slope of the voltage on GATE is set by an external capacitor connected from GATE to GND and an internal 32µA pull-up current source from the charge pump output.
PAGE 8
LT4256-3 W BLOCK DIAGRA VCC SENSE 16 15 + OPEN CIRCUIT 3mV 4 OPEN – VP VP GEN FB 10 – 14mV TO 55mV CURRENT LIMIT CHARGE PUMP AND GATE DRIVER + + FOLDBACK REF GEN 2V 12 VOUT 13 GATE + – 3.99V 3.99V 7V 5 PWRGD 9 TIMER – 100k RETRY 7 UV 1 OV 2 VCC – INTERNAL UV 9.8V + 4V – UV 0.65V LOGIC + + TIMER LOW – VP – 108µA OV + 4V + TIMER HIGH 4.
PAGE 9
LT4256-3 TEST CIRCUIT OPEN 3V –+ 48V VCC PWRGD +– SENSE FB GATE OV VOUT UV TIMER RETRY GND 100pF 48V +– 3V +– 4256 F01 Figure 1 W UW TI I G DIAGRA S 4V 3.6V UV tPLHUV tPHLUV GATE VOUT +2V VOUT +2V 4256 F02 Figure 2. UV to GATE Timing 4.45V 3.99V FB tPLHFB PWRGD 1V tPHLFB 1V 4256 F03 Figure 3. VOUT to PWRGD Timing VCC – SENSE 55mV tPHLSENSE GATE VCC 4256 F04 Figure 4.
PAGE 10
LT4256-3 U W U U APPLICATIO S I FOR ATIO Hot Circuit Insertion When the power pins first make contact, transistor Q1 is held off. If the voltage on VCC is between the externally programmed undervoltage and overvoltage thresholds, VCC is above 9.8V and the voltage on TIMER is less than 4.65V (typ), transistor Q1 will be turned on (Figure 6).
PAGE 11
LT4256-3 U W U U APPLICATIO S I FOR ATIO To reduce inrush current, increase C1 or decrease load capacitance. If the voltage across the current sense resistor R5 reaches VSENSETRIP, the inrush current will be limited by the internal current limit circuitry. The voltage on GATE is adjusted to maintain a constant voltage across the sense resistor and TIMER begins to charge. noise spikes and capacitively coupled glitches from shutting down the LT4256-3 output erroneously.
PAGE 12
LT4256-3 U U W U APPLICATIO S I FOR ATIO Short-Circuit Protection The LT4256-3 features a programmable foldback current limit with an electronic circuit breaker that protects against short circuits or excessive load currents. The current limit is set by placing a sense resistor (R5) between VCC and SENSE.
PAGE 13
LT4256-3 U W U U APPLICATIO S I FOR ATIO TIMER TIMER provides a method for programming the maximum time the part is allowed to operate in current limit. When the current limit circuitry is not active, TIMER is pulled to GND by a 3µA current source. When the current limit circuitry becomes active, a 108µA pull-up current source is connected to TIMER and the voltage will rise with a slope equal to 105µA/CTIMER as long as the circuitry stays active.
PAGE 14
LT4256-3 U U W U APPLICATIO S I FOR ATIO Therefore, using RETRY only, the LT4256-3 will either latch off after an overcurrent fault condition or it will go into a hiccup mode. ⎛V ⎞ R8 = ⎜ THPWRGD – 1⎟ • R9, high to low ⎝ 3.99 V ⎠ 20kΩ ≤ R8 + R9 ≤ 200kΩ Power Good Detection ⎛ R8 ⎞ VTHPWRGD = 4.45V⎜ 1+ ⎟ , low to high ⎝ R9 ⎠ The LT4256-3 includes a comparator for monitoring the output voltage. The output voltage is sensed through the FB pin via an external resistor string.
PAGE 15
LT4256-3 U U W U APPLICATIO S I FOR ATIO This open FET condition can be falsely signalled during start-up if the load is not activated until after PWRGD goes high. To avoid this false indication, OPEN and PWRGD should not be polled for a period of time, tSTARTUP, given by: tSTARTUP = 3 • VCC • C1 32µA (9) This can be accomplished either by a microcontroller (if available) or by placing an RC filter as shown in Figure 13.
PAGE 16
LT4256-3 U U W U APPLICATIO S I FOR ATIO In some applications it may be possible for VOUT to ring below ground (due to the parasitic trace inductance). Higher current applications, especially where the output load is physically far away from the LT4256-3 will be more susceptible to these transients. This is normal and the LT4256-3 has been designed to allow for some ringing below ground.
PAGE 17
LT4256-3 U U W U APPLICATIO S I FOR ATIO In order to use this feature as designed, a bidirectional Zener diode is needed for D1. When the LT4256-3 commands the MOSFET off (and a bidirectional Zener is used), the output discharges very slowly (tOFF = (CLOAD • VOUT)/ 130µA). Several variations can be implemented to discharge the output faster. The recommeded method is shown in Figure 17 and uses an external PNP transistor, diode and resistor to discharge the output quickly.
PAGE 18
LT4256-3 U U W U APPLICATIO S I FOR ATIO Layout Considerations To achieve accurate current sensing, a Kelvin connection to the current sense resistor (R5 in typical application circuit) is recommended. Note that 1oz copper exhibits a sheet resistance of about 530µΩ/❏. Small resistances can cause large errors in high current applications. Noise immunity will be improved significantly by locating resistor dividers close to the pins with short VCC and GND traces.
PAGE 19
LT4256-3 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .0532 – .0688 (1.35 – 1.75) 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.
PAGE 20
LT4256-3 U U W U APPLICATIO S I FOR ATIO Dual 48V Supply Sequencing Application R5 0.020Ω Q2 IRF540 + D3 CMPZ5241BS 11V R1 64.9k VCC C1 R7 10nF 100Ω R6 10Ω GATE LT4256-3 VOUT UV C3 0.01µF SENSE R2 4.02k CL2 R8 36.5k VOUT2 48V 2A R4 51k R9 4.02k FB VIN 50V/DIV OV R3 4.02k OPEN PWRGD TIMER RETRY GND 33nF R5 0.020Ω VIN 48V UV R2 4.02k + D1 CMPZ5241BS 11V VCC R1 64.9k VOUT1 50V/DIV Q1 IRF540 D2 SMAT70A (SHORT PIN) C3 0.