Datasheet

LT4320/LT4320-1
7
4320fb
For more information www.linear.com/LT4320
applications inForMation
MOSFET Selection
A good starting point is to reduce the voltage drop of the
ideal bridge to 30mV per MOSFET with the LT4320 (50mV
per MOSFET with the LT4320-1). Given the average output
load current, I
AVG
, select R
DS(ON)
to be:
R
DS(ON)
=
30mV
I
AVG
for a DC power input
or
R
DS(ON)
=
30mV
3 •I
AVG
for an AC power input
In the AC power input calculation, 3 • I
AVG
assumes the
duration of current conduction occupies 1/3 of the AC
period.
Select the maximum allowable drain-source voltage, V
DSS
,
to be higher than the maximum input voltage.
Design Example
For a 24W, 12V DC/24V AC application, I
AVG
= 2A for 12V
DC. To cover the 12V DC case:
R
DS(ON)
=
30mV
2A
= 15mΩ
For the 24V AC operation, I
AVG
= 1A. To cover the 24V
AC case:
R
DS(ON)
=
30mV
3 • 1A
= 10mΩ
This provides a starting range of R
DS(ON)
values to choose
from.
Ensure the MOSFET can handle a continuous current of
3 • I
AVG
to cover the expected peak currents during AC rec-
tification. That is, select I
D
≥ 3A. Since a 24V AC waveform
can reach 34V peak, select a MOSFET with V
DSS
>>34V.
A good choice of V
DSS
is 60V in a 24V AC application.
Other Considerations in MOSFET Selection
Practical MOSFET considerations for the LT4320-based
ideal bridge application include selecting the lowest avail
-
able total gate charge (Q
g
) for the desired R
DS(ON)
. Avoid
oversizing the MOSFET, since an oversized MOSFET limits
the maximum operating frequency, creates unintended
efficiency losses, adversely increases turn-on/turn-off
times, and increases the total solution cost. The LT4320
gate pull-up/pull-down current strengths specified in the
Electrical Characteristics section, and the MOSFET total
gate charge (Q
g
), determine the MOSFET turn-on/off times
and the maximum operating frequency in an AC applica
-
tion. Choosing the lowest gate capacitance while meeting
R
DS(ON)
speeds up the response time for full enhancement,
regulation, turn-off and input shorting events.
V
GS(th)
must be a minimum of 2V or higher. A gate thresh-
old voltage lower than 2V is not recommended since too
much time is needed to discharge the gate below the
threshold and halt current conduction during a hot plug
or input short event.
C
LOAD
Selection
A 1μF ceramic and a 10μF minimum electrolytic capacitor
must be placed across the OUTP and OUTN pins with the
1µF ceramic placed as close to the LT4320 as possible.
Downstream power needs and voltage ripple tolerance
determine how much additional capacitance between
OUTP and OUTN is required. C
LOAD
in the hundreds to
thousands of microfarads is common.
A good starting point is selecting C
LOAD
such that:
C
LOAD
≥ I
AVG
/(V
RIPPLE
• 2 • Freq)
where I
AVG
is the average output load current, V
RIPPLE
is
the maximum tolerable output ripple voltage, and Freq
is the frequency of the input AC source. For example, in
a 60Hz, 24VAC application where the load current is 1A
and the tolerable ripple is 15V, choose C
LOAD
≥ 1A/(15V
• 2 • 60Hz) = 556µF.
C
LOAD
must also be selected so that the rectified output
voltage, OUTP-OUTN, must be within the LT4320/LT4320-1
specified OUTP voltage range.
Transient Voltage
Suppressor
For applications that may encounter brief overvoltage
events higher than the LT4320 absolute maximum rating,
install a unidirectional transient voltage suppressor (TVS)
between the OUTP and OUTN pins as close as possible
to the LT4320.