Datasheet

LT8582
12
8582f
OPERATION
Refer to the State Diagram (Figure 2) for the following
description of the LT8582’s operation during a fault
event. When a fault is detected on a channel, the LT8582
disables the CLKOUT pin for that channel, turns off the
power switches for that channel and the GATE pin for that
channel becomes high impedance. The external PMOS,
M1, is turned off by the external R
GATE
resistor (see
Block Diagram). With the external PMOS turned off, the
power path from V
IN
to V
OUT
is opened, protecting
power path components. Also, as soon as the feedback
voltage falls inside the range 65mV < FBX < 1.15V, PG
pulls low. Refer to Figure 4 for the case of an output short.
At the beginning of a fault event, a timeout sequence com-
mences where the SS pin for that channel is charged up to
1.84V (the SS pin will continue charging up to ~2.1V and
be held there in the case of a FAULT event that still exists)
and then discharged to 55mV. This timeout period relieves
the chip, the PMOS and other power path components
from electrical and thermal stress for a minimum amount
of time set by the voltage ramp rate on the SS pin.
Figure 4. Output Short-Circuit Protection of the LT8582
OPERATION – CURRENT LIMIT
The current limit operates independently of the FAULT
current limit. The current limit sets a maximum switch
current. This switch current limit is duty cycle dependent,
but for most applications will be around 3A minimum (see
the Electrical Characteristics). Once this limit is reached,
the switch duty cycle decreases, reducing the magnitude
of the output voltage. If, despite the reduced duty cycle
the switch current reaches the FAULT current limit, the part
will behave as described in the Operation – Fault section.
CLKOUT
5V/DIV
V
OUT1
5V/DIV
I
L1
5A/DIV
GATE
5V/DIV
20µs/DIV
8582 F04