Datasheet

LT8582
23
8582f
APPENDIX
INDEPENDENT CHANNELS
Either channel may be used independently of the other
channel. To disable one channel, drive SHDN of that channel
low. Activating or deactivating one channel will not alter
the functionality of the other channel.
SETTING THE OUTPUT VOLTAGE
The output voltage is set by connecting a resistor (R
FBX
)
from V
OUT
to the FBX pin. R
FBX
is determined by using
the following equation:
R
FBX
=
|V
OUT
–V
FBX
|
83.3µA
where V
FBX
is 1.204V (typical) for noninverting topologies
(i.e. boost and SEPIC regulators) and 7mV (typical) for
inverting topologies (see the Electrical Characteristics).
POWER SWITCH DUTY CYCLE
In order to maintain loop stability and deliver adequate
current to the load, the power NPNs (Q1 and Q2 in the
Block Diagram) cannot remain on for 100% of each clock
cycle. The maximum allowable duty cycle is given by:
DC
MAX
=
(T
P
–MinOffTime)
T
P
•100%
where T
P
is the clock period and MinOffTime (found in the
Electrical Characteristics) is typically 45ns.
Conversely, the power NPNs (Q1 and Q2 in the Block
Diagram) cannot remain off for 100% of each clock cycle
and will turn on for a minimum on time (MinOnTime) when
in regulation. This MinOnTime governs the minimum al-
lowable duty cycle given by:
DC
MIN
=
MinOnTime
T
P
•100%
Where T
P
is the clock period and MinOnTime (found in
the Electrical Characteristics) is typically 55ns.
The application should be designed such that the operating
duty cycle is between DC
MIN
and DC
MAX
.
Duty cycle equations for several common topologies are
given below where V
D
is the diode forward voltage drop
and V
CESAT
is the collector to emitter saturation voltage
of the switch. V
CESAT
, with SWA and SWB tied together, is
typically 270mV when the combined switch current (I
SWA
+ I
SWB
) is 2.75A.
For the boost topology (see Figure 5):
DC
BOOST
≅
V
OUT
–V
IN
+ V
D
V
OUT
+ V
D
–V
CESAT
For the SEPIC or dual inductor inverting topology (see
Figure 6 and Figure 7):
DC
SEPIC _& _INVERT
≅
|V
OUT
| +V
D
V
IN
+|V
OUT
| +V
D
–V
CESAT
For the single inductor inverting topology (see Figure 12):
DC
SI_INVERT
≅
|V
OUT
|–V
IN
+ V
CESAT
+ 3•V
D
|V
OUT
| +3•V
D
The LT8582 can be used in configurations where the duty
cycle is higher than DC
MAX
, but it must be operated in the
discontinuous conduction mode so that the effective duty
cycle is reduced.
INDUCTOR SELECTION
General Guidelines
The high frequency operation of the LT8582 allows for the
use of small surface mount inductors. For high efficiency,
choose inductors with high frequency core material,
such as ferrite, to reduce core losses. Also to improve
efficiency, choose inductors with more volume for a given
inductance. The inductor should have low DCR (copper-
wire resistance) to reduce I
2
R losses and must be able to
handle the peak inductor current without saturating. Note
that in some applications, the current handling require-
ments of the inductor can be lower, such as in the SEPIC
topology where each inductor only carries one half of the
total switch current. Multilayer chip inductors usually do
not have enough core volume to support peak inductor
currents in the 2A to 6A range. To minimize radiated noise,