Datasheet

LT8582
26
8582f
APPENDIX
and one at the input to the power path (see the equation
for C
PWR
in Table 1, Table 2 and Table 3). A 4.7F to 20F
input capacitor is sufficient for most applications.
Table 6 shows a list of several ceramic capacitor manufac-
turers. Consult the manufacturers for detailed information
on their entire selection of ceramic parts.
Table 6. Ceramic Capacitor Manufacturers
TDK www.tdk.com
Murata www.murata.com
Taiyo Yuden www.t-yuden.com
Kemet www.kemet.com
PMOS SELECTION
An external PMOS, controlled by the LT8582’s GATE pin,
can be used to facilitate input or output disconnect. The
GATE pin turns on the PMOS gradually during start-up
(see soft-start of external PMOS in the Operation section)
and turns the PMOS off when the LT8582 is in shutdown
or in fault.
The use of the external PMOS, controlled by the GATE pin,
is particularly beneficial when dealing with unintended
output shorts in a boost regulator. In a conventional boost
regulator, the inductor, Schottky diode and power switches
are susceptible to damage in the event of an output short.
Using an external PMOS in the boost regulator’s power
path (path from V
IN
to V
OUT
) controlled by the GATE pin,
will serve to disconnect the input from the output when
the output has a short. This helps to save the chip and
the other components in the power path from damage.
Ensure that both the diode and the inductor can survive
low duty cycle current pulses of 5 to 6 times their steady
state levels.
The PMOS chosen must be capable of handling the maxi-
mum input or output current depending on whether it is
used at the input or the output (see Figure 5).
Ensure that the PMOS is biased with enough source to
gate voltage (V
SG
) to enhance the device into the triode
mode of operation. The higher the V
SG
voltage that biases
the PMOS into triode, the lower the R
DSON
of the PMOS,
thereby lowering power dissipation in the device during
normal operation, as well as improving the efficiency of
the application. The following equations show the relation-
ship between R
GATE
(see Block Diagram) and the desired
V
SG
that the PMOS is biased with, where V
S
is the PMOS
source voltage:
V
GS
=
V
S
R
GATE
R
GATE
+ 2k
if V
GATE
< 2V
1m A t R
GATE
if V
GATE
≥ 2V
When using a PMOS, it is advisable to configure the specific
application for undervoltage lockout (see the Operations
section). The goal is to have V
IN
get to a certain minimum
voltage where the PMOS has sufficient V
SG
.
Figure 5 shows the PMOS connected in series with the
output to act as an output disconnect during a fault con-
dition. Using a PMOS with a high V
T
(~2V) can help to
reduce extraneous current spikes during hot-plug. The
resistor divider from V
IN
to the SHDN pin sets UVLO at
4V for this application.
Connecting the PMOS in series with the output offers cer-
tain advantages over connecting it in series with the input:
• Since the load current is always less than the input
current for a boost converter, the current rating of
the PMOS will be reduced.
• A PMOS in series with the output can be biased with
a higher overdrive voltage than a PMOS used in series
with the input, since V
OUT
> V
IN
. This higher overdrive
results in a lower R
DSON
rating for the PMOS, thereby
improving the efficiency of the regulator.
In contrast, an input connected PMOS works as a simple
hot-plug controller (covered in more detail in the Hot-Plug
section). The input connected PMOS also functions as an
inexpensive means of protecting against multiple output
shorts in boost applications that synchronize the LT8582
with other compatible chips.