Datasheet

LT8616
11
8616fa
For more information www.linear.com/LT8616
OPERATION
Foreword
The LT8616 is a dual monolithic step down regulator. The
two channels differ in maximum current and input range.
The following sections describe the operation of channel
1 and common circuits. They will highlight channel 2 dif
-
ferences and
interactions only when relevant. To
simplify
the application, both V
IN1
and V
IN2
are assumed to be con-
nected to the same input supply. However, note that V
IN1
must be greater than 3.4V for either channel to operate.
Operation
The LT8616 is a dual monolithic, constant frequency, peak
current mode step-down DC/DC converter.
An oscillator, with frequency set using a resistor on the RT
pin, turns on the internal top power switch at the beginning
of each clock cycle. Current in the inductor then increases
until the top switch current comparator trips and turns off
the top power switch. The peak inductor current at which
the top switch turns off is controlled by the voltage on the
internal V
C
node. The error amplifier servos the V
C
node
by comparing the voltage on the FB pin with an internal
0.790V reference. When the load current increases it causes
a reduction in the feedback voltage relative to
the reference,
causing the error amplifier to raise the V
C
voltage until the
average inductor current matches the new load current.
When the top power switch turns off, the synchronous
power switch turns on until the next clock cycle begins or
inductor current falls to zero. If overload conditions result
in more than the valley current limit flowing through the
bottom switch, the next clock cycle will be delayed until
current returns to a safe level.
If either EN/UV pin is low, the corresponding channel is
shut down. If both EN/UV pins are low, the LT8616 is
fully shut down and draws 1.7µA from the input supply.
When the EN/UV pins are above 1.03V, the corresponding
switching regulators will become active. 1.3μA is supplied
by V
IN1
to common bias circuits for both channels.
Each channel can independently enter Burst Mode opera-
tion to
optimize efficiency at light load. Between bursts,
all
circuitry associated with controlling the output switch
is shut down, reducing the channel's contribution to in
-
put supply current. In a typical application, 6.5μA will be
consumed from the input supply when regulating both
channels with no load. Ground the SYNC/MODE pin
for
Burst
Mode operation or apply a DC voltage above 2.4V
to use pulse-skipping mode. If a clock is applied to the
SYNC/MODE pin, both channels will synchronize to the
external clock frequency and operate in pulse-skipping
mode. While in pulse-skipping mode the oscillator operates
continuously and SW transitions are aligned to the clock.
During light loads, switch pulses are skipped to regulate
the output and the quiescent current per channel will be
several hundred µA.
To improve efficiency across all loads, supply current to
internal circuitry can be sourced from the BIAS pin when
biased at 3.1V or above. Otherwise, the internal circuitry
will draw current exclusively from V
IN1
. The BIAS pin
should be connected to the lowest V
OUT
programmed at
3.3V or above.
Comparators monitoring the FB pin voltage will pull the
corresponding PG pin low if the output voltage varies
more than ±10% (typical) from the regulation voltage or
if a fault condition is present.
Tracking soft-start is implemented by providing constant
current via the TR/SS pin to an external soft-start capaci
-
tor to
generate a voltage ramp. FB voltage is regulated to
the
voltage at the TR/SS pin until it exceeds 0.790V; FB
is then regulated to the 0.790V reference. Soft-start also
reduces
the valley current limit to avoid inrush current
during start-up. The SS capacitor is reset during shutdown,
V
IN1
undervoltage, or thermal shutdown.
Channel 1 is designed for 1.5A load, whereas channel 2
is designed for 2.5A load. Channel 1 has a minimum V
IN1
requirement of 3.4V, but channel 2 can operate with no
minimum V
IN2
provided that the minimum V
IN1
has been
satisfied.
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