LTC1090 Single Chip 10-Bit Data Acquisition System U FEATURES ■ ■ ■ ■ ■ DESCRIPTIO Software Programmable Features: Unipolar/Bipolar Conversions 4 Differential/8 Single Ended Inputs MSB or LSB First Data Sequence Variable Data Word Length Built-In Sample and Hold Single Supply 5V, 10V or ±5V Operation Direct 4 Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports 30kHz Maximum Throughput Rate U KEY SPECIFICATIO S ■ ■ ■ ■ Resolution: 10 Bits Total Unadjusted Error (LTC1090A): ±1/2LSB Max
LTC1090 W W W AXI U U U W PACKAGE/ORDER I FOR ATIO U ABSOLUTE RATI GS (Notes 1 and 2) Supply Voltage (VCC) to GND or V – ................................ 12V Negative Supply Voltage (V –) ..................... – 6V to GND Voltage: Analog and Reference Inputs .................................... (V –) –0.3V to VCC 0.3V Digital Inputs ......................................... –0.3V to 12V Digital Outputs .............................. – 0.3V to VCC 0.3V Power Dissipation ..............................
LTC1090 W U U CO VERTER A D ULTIPLEXER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 3) MIN LTC1090A TYP CONDITIONS MAX UNITS Offset Error (Note 4) ● ±0.5 ±0.5 LSB Linearity Error (Notes 4 and 5) ● ±0.5 ±0.5 LSB Gain Error (Note 4) ● ±1.0 ±2.0 LSB Total Unadjusted Error VREF = 5.000V (Notes 4 and 6) ● ±1.
LTC1090 U DIGITAL A D DC ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specification are TA = 25°C. (Note 3) MIN LTC1090/LTC1090A TYP MAX SYMBOL PARAMETER CONDITIONS VIH High Level lnput Voltage VCC = 5.25V ● VIL Low Level Input Voltage VCC = 4.75V ● IIH High Level lnput Current VIN = VCC ● 2.5 µA IIL Low Level Input Current VIN = 0V ● –2.5 µA VOH High Level Output Voltage VCC = 4.
LTC1090 TEST CIRCUITS On and Off Channel Leakage Current Voltage Waveforms for DOUT Delay Time, tdDO SCLK 5V 0.8V ION tdDO A ON CHANNELS 2.4V 0.4V DOUT IOFF A Voltage Waveforms for DOUT Rise and Fall Times, tr, tf OFF CHANNELS POLARITY 2.4V 0.4V DOUT LTC1090 • TC01 tf tr LTC1090 • TC02 Voltage Waveforms for ten and tdis 1 2 ACLK 2.0V CS DOUT WAVEFORM 1 (SEE NOTE 1) 90% 2.4V ten DOUT WAVEFORM 2 (SEE NOTE 2) tdis 0.
LTC1090 U U U PI FU CTIO S # PIN FUNCTION DESCRIPTION 1-8 9 CH0 to CH7 COM Analog Inputs Common 10 11 12 13,14 15 16 17 18 19 20 DGND AGND V– REF –, REF+ CS DOUT DIN SCLK ACLK VCC Digital Ground Analog Ground Negative Supply Reference Inputs Chip Select Input Digital Data Output Data Input Shift Clock A/D Conversion Clock Positive Supply The analog inputs must be free of noise with respect to AGND. The common pin defines the zero reference point for all single ended inputs.
LTC1090 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage Supply Current vs Temperature 4 3 2 1.2 1.0 0.8 0.6 1 0 0.6 REF +OPEN ACLK = 2MHz CS = 5V VCC = 5V 0.4 4 5 9 6 7 8 SUPPLY VOLTAGE, VCC (V) 0.2 50 100 –50 –25 25 75 0 AMBIENT TEMPERATURE, TA (°C) 10 LTC1090 • TPC01 OFFSET ERROR (LSBs = 6 8 7 VOS = 1mV 4 3 VOS = 0.5mV 0 0.5 LTC1090 • TPC03 1 3 4 2 REFERENCE VOLTAGE, VREF (V) 0 5 0.5 0 0 0.5 0.
LTC1090 U W 0.6 VCC = 5V VREF = 5V ACLK = 2MHz 0.5 0.4 0.3 0.2 0.1 0 50 100 –50 –25 25 75 0 AMBIENT TEMPERATURE, TA (°C) 125 0.6 VCC = 5V VREF = 5V ACLK = 2MHz 0.5 0.4 0.3 0.2 0.
LTC1090 U W TYPICAL PERFOR A CE CHARACTERISTICS Digital Input Logic Threshold vs Supply Voltage Input Channel Leakage Current vs Temperature 1000 INPUT CHANNEL LEAKAGE CURRENT (nA) TA = 25°C 3 2 1 5 6 7 8 9 SUPPLY VOLTAGE, VCC (V) GUARANTEED 800 700 600 500 400 ON CHANNEL 300 200 OFF CHANNELS 100 0 4 LTC1090 NOISE = 200µV PEAK-TO-PEAK 900 PEAK-TO-PEAK NOISE ERROR (LSBs) 4 LOGIC THRESHOLD (V) Noise Error vs Reference Voltage 2.
LTC1090 U W U U APPLICATIO S I FOR ATIO Data transfer is initiated by a falling chip select (CS) signal. After the falling CS is recognized, an 8-bit input word is shifted into the DIN input which configures the LTC1090 for the next conversion. Simultaneously, the result of the previous conversion is output on the DOUT line. At the end of the data exchange the requested conversion begins and CS should be brought high.
LTC1090 U W U U APPLICATIO S I FOR ATIO 4 Differential 8 Single Ended CHANNEL 0 1 2 3 4 5 6 7 CHANNEL 0,1 +( – ) –( + ) 2,3 +( – ) –( + ) 4,5 +( – ) –( + ) 6,7 +( – ) –( + ) Combinations of Differential and Single Ended CHANNEL + + + + + + + + 0,1 + – 2,3 – + 4 5 6 7 COM ( – ) + + + + COM ( – ) LTC1090 • AI04B LTC1090 • AI04A LTC1090 • AI04C Changing the MUX Assignment “On the Fly” 4,5 + – 6,7 + – – + 5,4 6 7 + + COM ( – ) COM (UNUSED) 2ND CONVERSION 1ST CONVERSION LTC10
LTC1090 U W U U APPLICATIO S I FOR ATIO Unipolar Output Code (UNI = 1) OUTPUT CODE INPUT VOLTAGE INPUT VOLTAGE (VREF = 5V) 1111111111 1111111110 • • • 0000000001 0000000000 VREF – 1LSB VREF – 2LSB • • • 1LSB 0V 4.9951V 4.9902V • • • 0.0049V 0V control the length of the present, not the next, DOUT word. WL1 and WL0 are never “don’t cares” and must be set for the correct DOUT word length even when a “dummy” DIN word is sent.
LTC1090 U W U U APPLICATIO S I FOR ATIO 8-Bit Word Length t SMPL t CONV CS SCLK 1 8 (SB) DOUT MSB FIRST B9 B8 B7 B6 B5 B4 B3 B2 DOUT LSB FIRST B0 B1 B2 B3 B4 B5 B6 B7 THE LAST TWO BITS ARE TRUNCATED LTC1090 • AI08A 10-Bit Word Length t SMPL t CONV CS SCLK 10 1 (SB) DOUT MSB FIRST B9 B8 B7 B6 B5 B4 B3 B2 B1 DOUT LSB FIRST B0 B1 B2 B3 B4 B5 B6 B7 B8 B0 (SB) B9 LTC1090 • AI08B 12-Bit Word Length t CONV t SMPL CS SCLK 10 1 12 (SB) DOUT MSB FIRST B
LTC1090 U W U U APPLICATIO S I FOR ATIO 4. CS Low During Conversion In the normal mode of operation, CS is brought high during the conversion time (see Figure 3). The serial port ignores any SCLK activity while CS is high. The LTC1090 will also operate with CS low during the conversion. In this mode, SCLK must remain low during the conversion as shown in Figure 4.
LTC1090 U W U U APPLICATIO S I FOR ATIO serial formats (see Table 2). If an MPU without a serial interface is used, then 4 of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1090. Included here are three serial interface examples and one example showing a parallel port programmed to form the serial interface. Table 2.
LTC1090 U W U U APPLICATIO S I FOR ATIO Motorola SPI (MC68HC05C4) Hitachi Synchronous SCI (HD63705) The MC68HC05C4 transfers data MSB first and in 8-bit increments. Programming the LTC1090 for MSB first format and 16-bit word length allows the 10-bit data output to be received by the MPU as two 8-bit bytes with the final 6 unused bits filled with zeroes by the LTC1090. The HD63705 transfers serial data in 8-bit increments, LSB first.
LTC1090 U W U U APPLICATIO S I FOR ATIO 8051 Code Parallel Port Microprocessors When interfacing the LTC1090 to an MPU which has a parallel port, the serial signals are created on the port with software. Three MPU port lines are programmed to create the CS, SCLK and DIN signals for the LTC1090. A fourth port line reads the DOUT line. An example is made of the Intel 8051/8052/80C252 family. LOOP: Hardware and Software Interface to Intel 8051 Processor LTC1090 ANALOG INPUTS 8051 DOUT P1.
LTC1090 U W U U APPLICATIO S I FOR ATIO 6. Sharing the Serial Interface The LTC1090 can share the same 3-wire serial interface with other peripheral components or other LTC1090s (see Figure 5). In this case, the CS signals decide which LTC1090 is being addressed by the MPU. VCC 4.7µF TANTALUM 1 20 ANALOG CONSIDERATIONS 1. Grounding The LTC1090 should be used with an analog ground plane and single point grounding techniques. Pin 11 (AGND) should be tied directly to this ground plane.
LTC1090 U W U U APPLICATIO S I FOR ATIO 3. Analog Inputs “+” Input Settling Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1090 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. This input capacitor is switched onto the “+” input during the sample phase (tSMPL, see Figure 10).
LTC1090 U W U U APPLICATIO S I FOR ATIO Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figure 10). Again, the “+” and “–” input sampling times can be extended as described above to accommodate slower op amps.
LTC1090 U W U U APPLICATIO S I FOR ATIO MUX address bit is shifted in and continues during the remainder of the data transfer. On the falling edge of the final SCLK, the S&H goes into hold mode and the conversion begins. The voltage will be held on either the 8th, 10th, 12th or 16th falling edge of the SCLK depending on the word length selected. When driving the reference inputs, three things should be kept in mind: Differential Inputs 2.
LTC1090 U W U U VERTICAL: 0.5mV/DIV APPLICATIO S I FOR ATIO HORIZONTAL: 1µs/DIV Figure 16. Poor Reference Settling Can Cause A/D Errors 6. Reduced Reference Operation voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Unadjusted Offset Error vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 0.5mV which is 0.
LTC1090 U TYPICAL APPLICATIO A “Quick Look” Circuit for the LTC1090 SNEAK-A-BITTM Users can get a quick look at the function and timing of the LTC1090 by using the following simple circuit. REF+ and DIN are tied to VCC selecting a 5V input span, CH7 as a single ended input, unipolar mode, MSB first format and 16-bit word length. ACLK and SCLK are tied together and driven by an external clock. CS is driven at 1/64 the clock rate by the CD4520 and DOUT outputs the data.
LTC1090 U TYPICAL APPLICATIO Sneak-A-Bit Code for the LTC1090 Using the MC68HC05C4 SNEAK-A-BIT VIN 5V VIN MNEMONIC 5V ( + ) CH6 1ST CONVERSION 1024 STEPS ( – ) CH7 SOFTWARE 1ST CONVERSION VIN 0V 0V 2047 STEPS 0V 2ND CONVERSION 1024 STEPS ( – ) CH6 ( + ) CH7 –5V –5V 2ND CONVERSION SNEAK-A-BIT Code DOUT from LTC1090 in MC68HC05C4 RAM Sign Location $77 B10 B9 B8 B7 B6 B5 B4 B3 LSB B2 Location $87 B1 B0 filled with 0s DIN words for LTC1090 MSBF MUX Addr.
LTC1090 U PACKAGE DESCRIPTIO J Package 20-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) 1.060 (26.924) MAX CORNER LEADS OPTION (4 PLCS) 20 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 19 18 17 16 15 14 13 12 11 2 3 4 5 6 7 8 9 10 0.220 – 0.310 0.025 (5.588 – 7.874) (0.635) RAD TYP 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 1 0.005 (0.127) MIN 0.300 BSC (0.762 BSC) 0.200 (5.080) MAX 0.015 – 0.060 (0.381 – 1.524) 0.008 – 0.018 (0.203 – 0.
LTC1090 U PACKAGE DESCRIPTIO N Package 20-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) 1.040* (26.416) MAX 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 +0.889 8.255 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.020 (0.508) MIN 0.065 (1.651) TYP 0.125 (3.175) MIN 0.005 (0.
LTC1090 U PACKAGE DESCRIPTIO SW Package 20-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) 0.496 – 0.512* (12.598 – 13.005) 20 19 18 17 16 15 14 13 12 11 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 × 45° (0.254 – 0.737) 1 2 3 4 5 6 7 8 9 0.093 – 0.104 (2.362 – 2.642) 10 0.037 – 0.045 (0.940 – 1.143) 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) BSC 0.014 – 0.
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