Datasheet

22
LTC1091/LTC1092
LTC1093/LTC1094
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
Figure 8. “+” and “–” Input Settling Windows
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figure 8).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage settle completely during the first CLK cycle of the
conversion time and be free of noise. Minimizing R
SOURCE
–
and C2 will improve settling time. If large “–” input source
resistance must be used, the time allowed for settling can
be extended by using a slower CLK frequency. At the
maximum CLK rate of 500kHz, R
SOURCE
–
< 1k Ω and
C2 < 20pF will provide adequate settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 8). Again, the “+” and “–” input sampling times
can be extended as previously described to accommodate
slower op amps. Most op amps, including the LT1006 and
LT1013 single supply op amps, can be made to settle well
even with the minimum settling windows of 3µs (“+”
input) and 2µs (“–” input) which occur at the maximum
clock rate of 500kHz. Figures 9 and 10 show examples of
adequate and poor op amp settling.
CLK
D
IN
D
OUT
“+” INPUT
“–” INPUT
SAMPLE HOLD
“+” INPUT MUST
SETTLE DURING
THIS TIME
t
SMPL
t
CONV
CS
SGL/DIFFSTART MSBF
B9
1ST BIT TEST “–” INPUT MUST
SETTLE DURING THIS TIME
1091-4 F08
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