Datasheet

LTC1096/LTC1096L
LTC1098/LTC1098L
11
10968fc
PIN FUNCTIONS
LTC1096/LTC1096L
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1096/LTC1096L. A logic high on this
input disables the LTC1096/LTC1096L and disconnects the
power to the LTC1096/LTC1096L.
IN
+
(Pin 2): Analog Input. This input must be free of noise
with respect to GND.
IN
–
(Pin 3): Analog Input. This input must be free of noise
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
REF
(Pin 5): Reference Input. The reference input defi nes
the span of the A/D converter and must be kept free of
noise with respect to GND.
D
OUT
(Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the se-
rial data transfer.
V
CC
(Pin 8): Power Supply Voltage. This pin provides power
to the A/D converter. It must be free of noise and ripple by
bypassing directly to the analog ground plane.
LTC1098/LTC1098L
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1098/LTC1098L. A logic high on this
input disables the LTC1098/LTC1098L and disconnects the
power to the LTC1098/LTC1098L.
CH0 (Pin 2): Analog Input. This input must be free of noise
with respect to GND.
CH1 (Pin 3): Analog Input. This input must be free of noise
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
D
IN
(Pin 5): Digital Data Input. The multiplexer address
is shifted into this pin.
D
OUT
(Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the se-
rial data transfer.
V
CC
(V
REF
)(Pin 8): Power Supply Voltage. This pin provides
power and defi nes the span of the A/D converter. It must
be free of noise and ripple by bypassing directly to the
analog ground plane.