Datasheet

LTC1096/LTC1096L
LTC1098/LTC1098L
17
10968fc
Input Data Word
The LTC1096(L) requires no D
IN
word. It is permanently
confi gured to have a single differential input. The conver-
sion result, in which output on the D
OUT
line is MSB-fi rst
sequence, followed by LSB sequence providing easy
interface to MSB- or LSB-fi rst serial ports.
The LTC1098(L) clocks data into the D
IN
input on the ris-
ing edge of the clock. The input data words are defi ned
as follows:
Start Bit
The fi rst “logical one” clocked into the D
IN
input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1098(L) will ignore all leading zeros which
precede this logical one. After the start bit is received,
the remaining bits of the input word will be clocked in.
Further inputs on the D
IN
pin are then ignored until the
next CS cycle.
APPLICATIONS INFORMATION
CLK
CS
t
CYC
POWER
DOWN
t
suCS
t
WAKEUP
D
IN
SGL/
DIFF
MSBF
B0*
B1
B2
B3
B4B5
B6B7
NULL
BIT
Hi-Z
D
OUT
t
CONV
t
SMPL
HI-Z
START
ODD/
SIGN
DON'T CARE
MSB-FIRST DATA (MSBF = 0)
MSB-FIRST DATA (MSBF = 1)
10968 F02
CLK
CS
t
CYC
POWER
DOWN
t
suCS
t
WAKEUP
D
IN
SGL/
DIFF
MSBF
B0
B1B2
B3
B4B5
B6
B7
NULL
BIT
Hi-Z
D
OUT
t
CONV
t
SMPL
HI-Z
START
ODD/
SIGN
DON'T CARE
B7*B6B5
B4
B3B2B1
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
(MSB)
(MSB)
Figure 2. LTC1098(L) Operating Sequence Example: Differential Inputs (CH
+
, CH
–
)
SGL/
DIFF
ODD/
SIGN
MSBFSTART
MUX
ADDRESS
MSB-FIRST
/
LSB-FIRST
10968 AI02