Datasheet

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LTC1099

DESCRIPTIO

FEATURES

The LTC

1099 is a high speed microprocessor compatible

8-bit analog-to-digital converter (A/D). An internal sample-

and-hold (S/H) allows the A/D to convert inputs up to the

full Nyquist limit. With a conversion rate of 2.5µs, this

allows 156kHz 5V

P-P

input signals or slew rates as high as

2.5V/µs, to be digitized without the need for an external

S/H.

Two modes of operation, Read (RD) mode and Write-Read

(WR-RD) mode, allow easy interface with processors. All

timing is internal and edge sensitive which eliminates the

need for external pulse shaping circuits. The Stand-Alone

(SA) mode is convenient for those applications not involv-

ing a processor.

Data outputs are latched with three-state control to allow

easy interface to a processor data bus or I/O port. An

overflow output (OFL) is provided to allow cascading for

higher resolution.

■

Resolution: 8-Bits

■

Conversion Time: 2.5µs (RD Mode)

2.5µs (WR/RD Mode)

■

Slew Rate Limit (Internal S/H): 2.5V/µs

■

Low Power: 75mW Max

■

Total Unadjusted Error

LTC1099: ±1 LSB

LTC1099A: ±0.75 LSB

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

Built-In Sample-and-Hold

■

No Missing Codes

■

No User Trims Required

■

All Timing Inputs Edge Sensitive for Easy Processor

Interface

■

Fast Conversion Time: 2.5µs

■

Latched Three-State Outputs

■

Single 5V Operation

■

No External Clock

■

Overflow Output Allows Cascading

■

Input Allows User Adjustable Conversion Time

■

0.3" Wide 20-Pin PDIP

High Speed 8-Bit A/D

Converter with Built-In

Sample-and-Hold

INPUT FREQUENCY (kHz)

SIGNAL-TO-NOISE RATIO, SNR (dB)

–36

–38

–40

–42

–44

–46

–48

–50

–52

10 100

1099 G08

= 25°C

= 2.5µs

Infinite Hold Time Sample-and-Hold (T

ACQ

= 240ns) Signal-to-Noise Ratio (SNR) vs Input Frequency

KEY SPECIFICATIO S

TYPICAL APPLICATION

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

LTC1099

REF

–

SAMPLE

HOLD

IN V

MODE

WR/RDY

GND REF

–

REF

15 17

12 20

10k

2.5k

15V

–15V

OUT

LT1022AM6012

1099 TA01

Summary of content (16 pages)

PAGE 1
LTC1099 High Speed 8-Bit A/D Converter with Built-In Sample-and-Hold DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1099 is a high speed microprocessor compatible 8-bit analog-to-digital converter (A/D). An internal sampleand-hold (S/H) allows the A/D to convert inputs up to the full Nyquist limit. With a conversion rate of 2.5µs, this allows 156kHz 5VP-P input signals or slew rates as high as 2.5V/µs, to be digitized without the need for an external S/H.
PAGE 2
LTC1099 W W U W ABSOLUTE AXI U RATI GS (Notes 1, 2) Supply Voltage (VCC) to GND Voltage ...................... 12V Analog and Reference Inputs... – 0.3V to (VCC + 0.3V) Digital Inputs .........................................– 0.3V to 12V Digital Outputs ........................ – 0.3V to (VCC + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1099C/LTC1099AC ............................ 0°C to 70°C LTC1099I/LTC1099AI .......................
PAGE 3
LTC1099 U DIGITAL AND DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, REF+ = 5V, REF– = 0V and TA = TMIN to TMAX unless otherwise noted. LTC1099AI/LTC1099I MIN TYP MAX SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage All Digital Inputs, VCC = 5.25V ● VIL Low Level Input Voltage All Digital Inputs, VCC = 4.
PAGE 4
LTC1099 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Temperature 20 1.0 4 TA = 25°C TC = 2.5µs 18 LINEARITY ERROR (LBS) 3 14 12 10 8 6 2 1 4 0.7 0.6 0.5 0.4 0.3 0.1 25 – 25 0 50 75 100 AMBIENT TEMPERATURE, TA (°C) 0 0 125 0 1099 G01 Total Error vs Reference Voltage TA = 25°C TC = 2.5µs Accuracy vs Conversion Time CONVERSION TIME (µs) 2 1 0 RESISTOR BETWEEN PIN 19 AND VCC RESISTOR BETWEEN PIN 19 AND GND 1.0 0.
PAGE 5
LTC1099 U U U PIN FUNCTIONS VIN (Pin 1): Analog Input. DB0 to DB3 (Pins 2 to 5): Data Outputs. DB0 = LSB. INT (Pin 9): Output that goes low when the conversion in process is complete and goes high after data is read. GND (Pin 10): Ground Connection. WR/RDY (Pin 6): WR/RDY is an input when M0DE = VCC. Falling edge of WR switches internal S/H to hold then starts conversion. WR/RDY is an open drain output (active pull-down) when M0DE = GND.
PAGE 6
LTC1099 WU W TI I G DIAGRA S CS tP RD tRDY WR/RDY tCRD tINTH INT tACC0 DB0-DB7 t1H, t0H NEW DATA OLD DATA tACC2 1099 F02 Figure 2. RD Mode (Pin 7 Is GND) CS CS WR/RDY WR/RDY tP tCWR t CWR RD tP RD tINTH t INTH INT INT t ACC2 t1H, t0H DB0-DB7 t 1H, t 0H OLD DATA DB0-DB7 tACC2 t ACC0 1099 F03A Figure 3a. WR-RD Mode (Pin 7 Is HIGH and tRD > tCWR) Figure 3b.
PAGE 7
LTC1099 U U U FUNCTIONAL DESCRIPTIO Figure 5 shows the functional block diagram for the LTC1099 2-step flash ADC. It consists of two 4-bit flash converters, a 4-bit DAC and a differencing circuit. The conversion process proceeds as follows: VREF B7 MS 4-BIT FLASH VIN 1. At the start of the conversion, the on-board sampleand-hold switches from the sample to the hold mode. This is a true sample-and-hold with an acquisition time of 240ns, an aperture time of 110ns and a tracking rate of 2.5V/µs. 2.
PAGE 8
LTC1099 U U U FUNCTIONAL DESCRIPTIO T+ T–1 T–2 (+) TZ TZ VIN MS TAP DAC 0.5 LSB 0V LS TAP (–) C1 (–) VIRTUAL GROUND (+) (–) C2 C1 = C2 (–) HOLD TZ SAMPLE SAMPLE T+ T–1 T–2 STROBE 1099 F06 Figure 6. Six Input Switched Capacitor Comparator also that variations in the bias voltage with time and temperature will also be rejected. In this state, C1 charges to VIN. When TZ opens, VIN is held on C1. The next step is the first comparison — the MS-Flash.
PAGE 9
LTC1099 U DIGITAL I TERFACE The digital interface to the LTC1099 entails either controlling the conversion timing or reading data. There are two basic modes for controlling and reading the A/D — the Write-Read(WR-RD) mode and the Read (RD) mode. WR-RD Mode (Pin 7 = High) In the WR-RD mode, a conversion sequence starts on the falling edge of WR with CS low (Figures 3a and 3b). This is an edge-sensitive control function. The width of the WR input is not important.
PAGE 10
LTC1099 U U ANALOG INTERFACE The inclusion of a high quality sample-and-hold (S/H) simplifies the analog interface to the LTC1099. All of the error terms normally associated with an S/H (hold step, offset, gain and droop errors) are included in the error specifications for the A/D. This makes it easy for the designer since all the error terms need not be taken into account individually. S/H Timing A falling edge on the RD or WR input switches the S/H from acquire to hold and starts the conversion.
PAGE 11
LTC1099 U U ANALOG INTERFACE APPLICATIONS Note that since this is only a two quadrant multiplier, a carrier component (the input to the LTC1099) will appear in the output spectrum. Figure 11 shows the frequency spectrum of a 42.5kHz sine wave multiplied by a 5kHz sine wave. The depth of modulation is about 30dB. Figure 12 shows a 42.375kHz sine wave multiplied by a 30.875kHz sine wave. Note that at these higher frequencies, the depth of modulation is still about 30dB.
PAGE 12
LTC1099 U U ANALOG INTERFACE 10dBV/DIV 0 –70 32.5 34.5 36.5 38.5 40.5 37500Hz 42.5 44.5 42500Hz 46.5 48.5 50.5 47500Hz 52.5 1099 F11 Figure 11. Two Quadrant Multiplier Output Spectrum with 0V to 4.5V at 42.5kHz into LTC1099 and ±2V at 5kHz into DAC 10dBV/DIV 0 –70 5 15 11500Hz 25 35 45 30875Hz 42375Hz 55 65 75 73250Hz 85 95 105 1099 F12 Figure 12. Two Quadrant Multiplier Output Spectrum with 0V to 4.5V at 42.375kHz into LTC1099 and ±2V at 30.
PAGE 13
LTC1099 U TYPICAL APPLICATIONS TMS320C25 Interface Using RD Mode 5V (A10, B11, H2, L6) (K1) A0 (K2) A1 (L3) A2 (J11) IS (K3) A3 (B1, K11, L2) VSS 74AS138 VCC 5V TMS320C25 D4 D5 D6 D7 D0 D1 D2 READY (B8) (6) D3 STRB (H10) MSC (C10) (4) (3) (5) A VCC B Y0 C Y1 G2A Y2 G2B Y3 G1 Y4 Y7 Y5 GND Y6 (D1) (C2) (C1) (B2) LTC1099 ANALOG INPUT VOLTAGE (F1) (E2) (E1) (D2) (1) VIN VCC DB0 TC DB1 OFL DB2 DB7 DB3 DB6 WR/RDY DB5 MODE DB4 RD CS INT REF+ GND + C1 – REF C
PAGE 14
LTC1099 U TYPICAL APPLICATIONS TMS320C25 Interface Using WR/RD Mode 5V (A10, B11, H2, L6) (K1) A0 (K2) A1 (L3) A2 (J11) IS (K3) A3 VSS 74F138 VCC 5V TMS320C25 D0 (F1) ANALOG INPUT VOLTAGE (E2) D1 D2 D3 (E1) (D2) 5V READY (B8) MSC (C10) R/ W (H11) STRB A VCC B Y0 C Y1 G2A Y2 G2B Y3 G1 Y4 Y7 Y5 GND Y6 C5 0.
PAGE 15
LTC1099 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N Package 20-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 1.040* (26.416) MAX 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( 0.020 (0.508) MIN +0.035 0.325 –0.015 8.255 +0.889 –0.381 0.045 – 0.065 (1.143 – 1.651) ) 0.065 (1.651) TYP 0.005 (0.127) MIN 0.125 (3.
PAGE 16
LTC1099 U TYPICAL APPLICATIO S Cascading for 9-Bit Resolution CS 13 WR 8 CS LTC1099 WR/RDY VCC VIN 20 5V 1 VIN RD 6 B0 2 B1 3 µP B2 BUS B3 4 B4 14 B5 15 B6 16 B7 17 5 RD DB0 MODE DB1 VREF + 7 5V 12 5V DB2 4.7µF DB3 DB4 DB5 VREF – 11 4.7µF DB6 DB7 1k B8 OFL 18 OFL GND 10 5k 13 8 6 LTC1099 CS VCC WR/RDY VIN 4 5 14 15 16 17 18 5V 1k 1 RD 2 3 20 MODE DB0 VREF + 7 5V 12 DB1 DB2 4.