Datasheet

LTC1196/LTC1198
12
119698fb
BLOCK DIAGRAM
–
+
C
SMPL
BIAS AND
SHUTDOWN CIRCUIT
SERIAL PORT
V
CC
(V
CC
/V
REF
) CLK
D
OUT
IN
+
(CH0)
IN
–
(CH1)
HIGH SPEED
COMPARATOR
CAPACITIVE DAC
SAR
V
REF
(D
IN
)GND
PIN NAMES IN PARENTHESES
REFER TO THE LTC1198
CS
(CS/SHUTDOWN)
1196/98 BD
TEST CIRCUITS
On and Off Channel Leakage Current
5V
A
A
I
OFF
I
ON
POLARITY
OFF
CHANNEL
ON CHANNEL
1196/98 TC01
•
•
•
•
Load Circuit for t
dDO
, t
r
and t
f
D
OUT
1.4V
3k
100pF
TEST POINT
1196/98 TC02
Voltage Waveform for D
OUT
Rise and Fall Times, t
r
, t
f
Voltage Waveform for D
OUT
Delay Time, t
dDO
, t
hDO
D
OUT
V
OL
V
OH
t
r
t
f
1196/98 TC04
CLK
D
OUT
t
dDO
1196/98 TC03
V
IH
t
hDO
V
OH
V
OL