Datasheet

LTC1196/LTC1198
15
119698fb
APPLICATIONS INFORMATION
Connection to a microprocessor or a DSP serial port is
quite simple (see the Data Transfer section). It requires no
additional hardware, but the speed will be limited by the
clock rate of the microprocessor or the DSP which limits
the conversion time of the LTC1196/LTC1198.
Data Transfer
Data transfer differs slightly between the LTC1196 and
the LTC1198. The LTC1196 interfaces over three lines:
CS, CLK and D
OUT
. A falling CS initiates data transfer as
depicted by the LTC1196 Operating Sequence in Figure 1.
After CS falls, the fi rst CLK pulse enables D
OUT
. After two
null bits, the A/D conversion result is output on the D
OUT
line. Bringing CS HIGH resets the LTC1196 for the next
data exchange.
The LTC1198 can transfer data with three or four wires.
The additional input, D
IN
, is used to select the 2-channel
MUX confi guration.
The data transfer between the LTC1198 and the digital
systems can be broken into two sections: Input Data
Word and A/D Conversion Result. First, each bit of the
input data word is captured on the rising CLK edge by the
LTC1198. Second, each bit of the A/D conversion result
on the D
OUT
line is updated on the rising CLK edge by the
LTC1198. This bit should be captured on the next rising
CLK edge by the digital systems (see the A/D Conversion
Result section).
Data transfer is initiated by a falling chip select (CS) signal
as depicted by the LTC1198 Operating Sequence in Figure 2.
After CS falls, the LTC1198 looks for a START bit. After
the START bit is received, the 4-bit input word is shifted
into the D
IN
input. The fi rst two bits of the input word
confi gure the LTC1198. The last two bits of the input word
allow the ADC to acquire the input voltage by 2.5 clocks
before the conversion starts. After the conversion starts,
two null bits and the conversion result are output on the
D
OUT
line. At the end of the data exchange CS should be
brought HIGH. This resets the LTC1198 in preparation for
the next data exchange.
Input Data Word
The LTC1196 requires no D
IN
word. It is permanently con-
fi gured to have a single differential input. The conversion
result is output on the D
OUT
line in an MSB-fi rst sequence,
followed by zeros indefi nitely if clocks are continuously
applied with CS LOW.
The LTC1198 clocks data into the D
IN
input on the ris-
ing edge of the clock. The input data word is defi ned as
follows:
D
IN1
D
IN2
D
OUT1
D
OUT2
CS
SHIFT MUX
ADDRESS IN
2 NULL BITS
SHIFT A/D CONVERSION
RESULT OUT
1196/98 AI01
SGL/
DIFF
ODD/
SIGN
DUMMY
START
MUX
ADDRESS
DUMMY
BITS
119698 AI02
DUMMY
START Bit
The fi rst
logical one clocked into the D
IN
input after CS
goes LOW is the START bit. The START bit initiates the data
transfer. The LTC1198 will ignore all leading zeros which
precede this
logical one . After the START bit is received,
the remaining bits of the input word will be clocked in.
Further inputs on the D
IN
pin are then ignored until the
next CS cycle.
Multiplexer (MUX) Address
The two bits of the input word following the START bit as-
sign the MUX confi guration for the requested conversion.
For a given channel selection, the converter will measure
the voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table.
In single-ended mode, all input channels are measured
with respect to GND.
MUX ADDRESS
SGL/DIFF
1
1
0
0
ODD/SIGN
0
1
0
1
CHANNEL #
0
+
+
–
1
+
–
+
GND
–
–
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
1196/98 AI03
LTC1198 Channel Selection