Datasheet

LTC1196/LTC1198
16
119698fb
APPLICATIONS INFORMATION
Dummy Bits
The last two bits of the input word following the MUX ad-
dress are dummy bits. Either bit can be a
logical one or a
logical zero . These two bits allow the ADC 2.5 clocks to
acquire the input signal after the channel selection.
A/D Conversion Result
Both the LTC1196 and the LTC1198 have the A/D conver-
sion result appear on the D
OUT
line after two null bits (see
the operating sequences in Figures 1 and 2). Data on the
D
OUT
line is updated on the rising edge of the CLK line.
The D
OUT
data should also be captured on the rising CLK
edge by the digital systems. Data on the D
OUT
line remains
valid for a minimum time of t
hDO
(30ns at 5V) to allow the
capture to occur (see Figure 3).
Unipolar Transfer Curve
The LTC1196/LTC1198 are permanently confi gured for
unipolar only. The input span and code assignment for this
conversion type are shown in the following fi gures.
CLK
V
IH
t
dDO
D
OUT
1196/98 TC03
V
OH
V
OL
t
hDO
Figure 3. Voltage Waveform for D
OUT
Delay Time, t
dDO
and t
hDO
Unipolar Transfer Curve
0V 1LSB
V
REF
–
2LSB
V
REF
–
1LSB
V
REF
V
IN
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
•
•
•
1196/98 AI04
Unipolar Output Code
OUTPUT CODE
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
•
•
•
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
INPUT VOLTAGE
V
REF
– 1LSB
V
REF
– 2LSB
•
•
•
1LSB
0V
INPUT VOLTAGE
(V
REF
= 5.000V)
4.9805V
4.9609V
•
•
•
0.0195V
0V
1196/98 AI05
1
2 3 4
CLK
DATA (D
IN
/D
OUT
)
START SGL/DIFF ODD/SIGN
DUMMY BITS LATCHED
BY LTC1198
LTC1198 CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO THE DIGITAL SYSTEM
THE DIGITAL SYSTEM CONTROLS DATA LINE
AND SENDS MUX ADDRESS TO LTC1198
THE DIGITAL SYSTEM MUST RELEASE DATA LINE AFTER
5TH RISING CLK AND BEFORE THE 5TH FALLING CLK
LTC1198 TAKES CONTROL OF
DATA LINE ON 5TH FALLING CLK
CS
1196/98 F04
5
DUMMY
Figure 4. LTC1198 Operation with D
IN
and D
OUT
Tied Together
Operation with D
IN
and D
OUT
Tied Together
The LTC1198 can be operated with D
IN
and D
OUT
tied
together. This eliminates one of the lines required to com-
municate to the digital systems. Data is transmitted in both
directions on a single wire. The pin of the digital systems
connected to this data line should be confi gurable as either
an input or an output. The LTC1198 will take control of
the data line and drive it LOW on the fi fth falling CLK edge
after the START bit is received (see Figure 4). Therefore,
the port line of the digital systems must be switched to
an input before this happens to avoid a confl ict.