Datasheet

LTC1196/LTC1198
19
119698fb
APPLICATIONS INFORMATION
Single-Ended Inputs
The sample-and-hold of the LTC1198 allows conversion
of rapidly varying signals. The input voltage is sampled
during the t
SMPL
time as shown in Figure 7. The sampling
interval begins as the bit preceding the fi rst dummy bit
is shifted in and continues until the falling CLK edge after
the second dummy bit is received. On this falling edge, the
S&H goes into hold mode and the conversion begins.
Differential Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input
is still sampled and held and therefore may be rapidly
time varying just as in single-ended mode. However, the
voltage on the selected “–” input must remain constant
and be free of noise and ripple throughout the conversion
time. Otherwise, the differencing operation may not be
performed accurately. The conversion time is 8.5 CLK
cycles. Therefore, a change in the “–” input voltage during
this interval can cause conversion errors. For a sinusoidal
voltage on the “–” input, this error would be:
V
ERROR(MAX)
= V
PEAK
• 2 • π • f(–) • 8.5/fCLK
where f(“–”) is the frequency of the “–” input voltage, V
PEAK
is its peak amplitude and f
CLK
is the frequency of the CLK.
V
ERROR
is proportional to f(–) and inversely proportional
to f
CLK
. For a 60Hz signal on the “–” input to generate a
1/4LSB error (5mV) with the converter running at CLK =
12MHz, its peak value would have to be 18.7V.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1196/LTC1198
have one capacitive switching input current spike per
conversion. These current spikes settle quickly and do
not cause a problem. However, if source resistances larger
than 100Ω are used or if slow settling op amps drive the
inputs, care must be taken to insure that the transients
caused by the current spikes settle completely before the
conversion begins.
“+” Input Settling
The input capacitor of the LTC1196 is switched onto
“+” input at the end of the conversion and samples the
input signal until the conversion begins (see Figure 1).
The input capacitor of the LTC1198 is switched onto “+”
input during the sample phase (t
SMPL
, see Figure 7). The
sample phase is 2.5 CLK cycles before conversion starts.
The voltage on the “+” input must settle completely within
t
SMPL
for the LTC1196/LTC1198. Minimizing R
SOURCE
+
will improve the input settling time. If a large “+” input
source resistance must be used, the sample time can be
increased by allowing more time between conversions
for the LTC1196 or by using a slower CLK frequency for
the LTC1198.
“–” Input Settling
At the end of the t
SMPL
, the input capacitor switches to the
“–” input and conversion starts (see Figures 1 and 7). During
the conversion, the “+” input voltage is effectively “held”
by the sample-and-hold and will not affect the conversion
result. However, it is critical that the “–” input voltage settle
completely during the fi rst CLK cycle of the conversion time
and be free of noise. Minimizing R
SOURCE
–
will improve
settling time. If a large “–” input source resistance must
be used, the time allowed for settling can be extended by
using a slower CLK frequency.
Input Op Amps
When driving the analog inputs with an op amp it is im-
portant that the op amp settle within the allowed time (see
Figures 1 and 7). Again, the “+” and “–” input sampling
times can be extended as described above to accommodate
slower op amps.
To achieve the full sampling rate, the analog input should
be driven with a low impedance source (<100Ω) or a
high speed op amp (e.g., the LT1223, LT1191 or LT1226).
Higher impedance sources or slower op amps can easily
be accommodated by allowing more time for the analog
input to settle as described above.