Datasheet

LTC1196/LTC1198
24
119698fb
TYPICAL APPLICATIONS
Interfacing the LTC1198 to the TMS320C25 DSP
Figure 15 illustrates the interface between the LTC1198
8-bit data acquisition system and the TMS320C25 digital
signal processor (DSP). The interface, which is optimized
for speed of transfer and minimum processor supervision,
can complete a conversion and shift the data in 4μs with
f
CLK
= 5MHz. The cycle time, 4μs, of each conversion is
limited by maximum clock frequency of the serial port of
the TMS320C25 which is 5MHz. The supply voltage for
the LTC1198 in Figure 15 can be 2.7V to 6V with f
CLK
=
5MHz. At 2.7V, f
CLK
= 5MHz will work at 25°C. See the
Recommended Operating Conditions table in the Electrical
Characteristics section for limits over temperature.
Hardware Description
The circuit works as follows: the LTC1198 clock line
controls the A/D conversion rate and the data shift rate.
Data is transferred in a synchronous format over D
IN
and
D
OUT
. The serial port of the TMS320C25 is compatible
with that of the LTC1198. The data shift clock lines (CLKR,
CLKX) are inputs only. The data shift clock comes from
an external source. Inverting the shift clock is necessary
because the LTC1198 and the TMS320C25 clock the input
data on opposite edges.
The schematic of Figure 15 is fed by an external clock
source. The signal is fed into the CLK pin of the LTC1198
directly. The signal is inverted with a 74HC04 and then
applied to the data shift clock lines (CLKR, CLKX). The
framing pulse of the TMS320C25 is fed directly to the CS
of the LTC1198. DX and DR are tied directly to D
IN
and
D
OUT
, respectively.
70 140 210 280 350 420 490
560
630
700
770 840 910 980 1050 1120
DATA
CLK
CS
B7
B4
B6
B5
B3
B1
B2
B0
TIME (ns)
1196/98 F14
Figure 14. The Timing Diagram
1196/98 F15
5MHz CLK
CLKX
CLKR
FSR
FSX
DX
DR
CLK
LTC1198
TMS320C25
CS
D
IN
D
OUT
CH0
CH1
Figure 15. Interfacing the LTC1198 to the TMS320C25 DSP